时序逻辑电路（3）----------计数器
【例9.23】可变模加法/减法计数器module updown_count(d,clk,clear,load,up_down,qd);
input d;
input clk,clear,load;
input up_down;
output qd;
reg cnt;
assign qd = cnt;
always @(posedge clk)
begin
if (!clear) cnt = 8'h00; //同步清0，低电平有效
elseif (load) cnt = d; //同步预置
elseif (up_down)cnt = cnt + 1; //加法计数
else cnt = cnt - 1; //减法计数
end
endmodule
【例9.24】4位Johnson计数器（异步复位）
module johnson(clk,clr,out);
input clk,clr;
output out;
reg out;
always @(posedge clk or posedge clr)
begin
if (clr) out<= 4'h0;
else
beginout<= out<< 1;
out<= ~out;
end
end
endmodule
【例3.2】4位计数器
module count4(out,reset,clk);
output out;
input reset,clk;
reg out;
always @(posedge clk)
begin
if (reset)out<=0; //同步复位
else out<=out+1; //计数
end
endmodule
【例5.2】同步置数、同步清零的计数器
module count(out,data,load,reset,clk);
output out;
input data;
input load,clk,reset;
reg out;
always @(posedge clk) //clk上升沿触发
begin
if (!reset) out = 8'h00; //同步清0，低电平有效
else if (load) out = data; //同步预置
else out = out + 1; //计数
end
endmodule
【例5.11】模为60的BCD码加法计数器
module count60(qout,cout,data,load,cin,reset,clk);
output qout;
output cout;
input data;
input load,cin,clk,reset;
reg qout;
always @(posedge clk) //clk上升沿时刻计数
begin
if (reset) qout<=0; //同步复位
elseif(load) qout<=data; //同步置数
elseif(cin)
begin
if(qout==9) //低位是否为9，是则
begin
qout<=0; //回0，并判断高位是否为
if (qout==5)qout<=0;
else
qout<=qout+1; //高位不为5，则加1
end
else //低位不为9，则加1
qout<=qout+1;
end
end
assign cout=((qout==8'h59)&cin)?1:0; //产生进位输出信号
endmodule 【例6.1】加法计数器中的进程
module count(data,clk,reset,load,cout,qout);
output cout;
output qout;
reg qout;
input data;
input clk,reset,load;
always @(posedge clk) //进程1，always过程块
begin
if (!reset) qout= 4'h00; //同步清0，低电平有效
else if (load) qout= data; //同步预置
else qout=qout + 1; //加法计数
end
assign cout=(qout==4'hf)?1:0; //进程2，用持续赋值产生进位信号
【例7.3】行为描述方式实现的4位计数器
module count4(clk,clr,out);
input clk,clr;
output out;
reg out;
always @(posedge clk or posedge clr)
begin
if (clr) out<=0;
else out<=out+1;
end
endmodule
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