Verilog设计练习进阶（2）-------简单的时序逻辑设计
简单的二分频设计，二分频简单的布局布线以后，就是由简单的D触发器实现的。module verilog_prj(reset,clk_in,clk_out);
input clk_in,reset;
output clk_out;
reg clk_out;
always @(posedge clk_in)
begin
if(!reset)clk_out=0;
else clk_out=~clk_out;
end
endmodule
仿真测试模块
`timescale 1 ns/ 1 ps
module verilog_prj_vlg_tst();
// test vector input registers
reg clk_in;
reg reset;
// wires
wire clk_out;
// assign statements (if any)
verilog_prj i1 (
// port map - connection between master ports and signals/registers
.clk_in(clk_in),
.clk_out(clk_out),
.reset(reset)
);
always#50clk_in = ~clk_in;
initial
begin
clk_in = 0;
reset = 1;
#100 reset = 0;
#100 reset = 1;
#10000 $stop;
#10000 $stop;
end RTL视图
功能仿真
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