CPLD570实验二:按键滤波检测
说明:1. 发现有些工程做仿真有点麻烦,还是直接下载到CPLD里面比较方便。2.不过作为初学者,还是试着写了个一个功能仿真。
3. 这里有一个很重要的方法,就是脉冲边沿检测法,这个方法很好,需要好好掌握。
module KEY(
clk,
key,
led
);
inputkey;
outputled;
input clk;
/*
********************************************************************
* 脉冲边沿检测,只要出现下降沿就产生一个高脉冲
********************************************************************
*/
reg key_value;
always @(posedge clk )
begin
key_value <= key;
end
reg key_value_r;
always @ ( posedge clk)
begin
key_value_r <= key_value;
end
//当寄存器key_value由1变为0时,led_edge的值变为高,维持一个时钟周期
wire key_edge = key_value_r & ( ~key_value);
/*
********************************************************************
* 脉冲边沿检测,只要出现下降沿就产生一个高脉冲
********************************************************************
*/
regcnt; //计数寄存器
always @ (posedge clk)
begin
if(key_edge) cnt <=20'd0;
else cnt <= cnt + 1'b1;
end
reg low_sw;
always @(posedge clk)
if (cnt == 20'hfffff)
low_sw <= key;
//每个时钟周期的上升沿将low_sw信号锁存到low_sw_r中
reg low_sw_r;
always @ (posedge clk)
low_sw_r <= low_sw;
//当寄存器low_sw由1变为0时,led_ctrl的值变为高,维持一个时钟周期
wire led_ctrl = low_sw_r & ( ~low_sw);
/*
********************************************************************
* 实现LED的翻转功能
********************************************************************
*/
reg d1=0;
reg d2=0;
reg d3=0;
reg d4=0;
reg d5=0;
reg d6=0;
always @ (posedge clk)
begin //某个按键值变化时,LED将做亮灭翻转
if ( led_ctrl ) d1 <= ~d1;
if ( led_ctrl ) d2 <= ~d2;
if ( led_ctrl ) d3 <= ~d3;
if ( led_ctrl ) d4 <= ~d4;
if ( led_ctrl ) d5 <= ~d5;
if ( led_ctrl ) d6 <= ~d6;
end
assign led = d1 ? 1'b1 : 1'b0; //LED翻转输出
assign led = d2 ? 1'b1 : 1'b0;
assign led = d3 ? 1'b1 : 1'b0;
assign led = d4 ? 1'b1 : 1'b0;
assign led = d5 ? 1'b1 : 1'b0;
assign led = d6 ? 1'b1 : 1'b0;
endmodule
测试模块,功能仿真的结果有点问题
`timescale 1 ns/ 1 ps
`define clk_cycle 10
module KEY_vlg_tst();
// test vector input registers
reg clk;
reg key;
// wires
wire led;
// assign statements (if any)
KEY i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.key(key),
.led(led)
);
initial
begin
key = 6'b11_1111;
clk = 0;
#100_000_000 key = 6'b01_1111;
#50_000_000key = 6'b11_1111;
#50_000_000$stop;
end
always#`clk_cycleclk = ~clk;
endmodule
功能仿真没有检测到有按键按下,以后有时间再做,实际测试是没问题的。
页:
[1]