CPLD570实验四：ADC
顶层原理图Re:CPLD570实验四：ADC TLC549
module adc(
nADCCLK_100KHz, //TLC549 clk
ADC_DataIN, //TLC549 data in
nADC_CS, //AD TLC549 cs
ADC_DataOUT //TLC549 data out
);
input ADC_DataIN;
output ADC_DataOUT;
output nADC_CS;
inputnADCCLK_100KHz;
/* used for ADC */
reg nADC_CS;
regcnt;
regdataout;
reg ADC_DataOUT;
/* used for FSM */
regstate;
parameter sample = 2'b00,
display = 2'b01;
/*
**********************************************
ADC Program
**********************************************
*/
always@(negedge nADCCLK_100KHz)
begin
case(state)
sample:
begin
nADC_CS <= 1'b0;
dataout <= {dataout, ADC_DataIN};
if(cnt > 4'd7)
begin
cnt <= 4'd0;
state<=display;
end
else
begin
cnt <= cnt + 1'b1;
state <= sample;
end
end
display:
begin
nADC_CS <= 1'b1; //关AD片选
ADC_DataOUT <= dataout;
//得到采集的数据
state<=sample;
end
default: state<=display;
endcase
end
endmodule
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