1. Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "q[0]" is stuck at GND
Warning (13410): Pin "q[1]" is stuck at VCC
这个是因为输出引脚是个常数的原因,举一个例子:
module block(clk, q);
input clk;
output[1:0] q;
reg[1:0] q;
reg a;
reg b = 1'b1;
always @(posedge clk)
begin
a = b;
q = a + 1'b1; //得到的q就是一个常熟值2
end
endmodule
对应的RTL视图如下
2. Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "clk"
还以上面的例子为例子,看下上面的那个RTL视图,不管CLK如何变化,输入永远是2,所以会有这个警告
Error (209015): Can't configure device. Expected JTAG ID code 0x020A10DD for device 1, but found JTAG ID code 0x020A20DD.
出现这个错误是因为目标期间和实际现在的期间不一致造成的。