注意函数HAL_RCC_DeInit，这个里面隐藏了个SysTick再次初始化
HAL_RCC_DeInit大家调用这个函数要特别注意：
**
* @briefResets the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - HSI ON and used as system clock source
* - HSE, PLL1, PLL2 and PLL3 OFF
* - AHB, APB Bus pre-scaler set to 1.
* - CSS, MCO1 and MCO2 OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_DeInit(void)
{
uint32_t tickstart;
/* Increasing the CPU frequency */
if(FLASH_LATENCY_DEFAULT> __HAL_FLASH_GET_LATENCY())
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
{
return HAL_ERROR;
}
}
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Set HSION bit */
SET_BIT(RCC->CR, RCC_CR_HSION);
/* Wait till HSI is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Set HSITRIM bits to the reset value */
SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6);
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
/* Update the SystemCoreClock and SystemD2Clock global variables */
SystemCoreClock = HSI_VALUE;
SystemD2Clock = HSI_VALUE;
/* Adapt Systick interrupt period */
if(HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
}
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till clock switch is ready */
while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */
CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON\
| RCC_CR_HSI48ON | RCC_CR_CSSHSEON);
/* Wait till HSE is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Clear PLLON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Reset PLL2ON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
/* Wait till PLL2 is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Reset PLL3 bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
/* Wait till PLL3 is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
#if defined(RCC_D1CFGR_HPRE)
/* Reset D1CFGR register */
CLEAR_REG(RCC->D1CFGR);
/* Reset D2CFGR register */
CLEAR_REG(RCC->D2CFGR);
/* Reset D3CFGR register */
CLEAR_REG(RCC->D3CFGR);
#else
/* Reset CDCFGR1 register */
CLEAR_REG(RCC->CDCFGR1);
/* Reset CDCFGR2 register */
CLEAR_REG(RCC->CDCFGR2);
/* Reset SRDCFGR register */
CLEAR_REG(RCC->SRDCFGR);
#endif
/* Reset PLLCKSELR register to default value */
RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
/* Reset PLLCFGR register to default value */
WRITE_REG(RCC->PLLCFGR, 0x01FF0000U);
/* Reset PLL1DIVR register to default value */
WRITE_REG(RCC->PLL1DIVR,0x01010280U);
/* Reset PLL1FRACR register */
CLEAR_REG(RCC->PLL1FRACR);
/* Reset PLL2DIVR register to default value */
WRITE_REG(RCC->PLL2DIVR,0x01010280U);
/* Reset PLL2FRACR register */
CLEAR_REG(RCC->PLL2FRACR);
/* Reset PLL3DIVR register to default value */
WRITE_REG(RCC->PLL3DIVR,0x01010280U);
/* Reset PLL3FRACR register */
CLEAR_REG(RCC->PLL3FRACR);
/* Reset HSEBYP bit */
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
/* Disable all interrupts */
CLEAR_REG(RCC->CIER);
/* Clear all interrupts flags */
WRITE_REG(RCC->CICR,0xFFFFFFFFU);
/* Reset all RSR flags */
SET_BIT(RCC->RSR, RCC_RSR_RMVF);
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLASH_LATENCY_DEFAULT< __HAL_FLASH_GET_LATENCY())
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
{
return HAL_ERROR;
}
}
return HAL_OK;
}
这个再次初始化会带来什么后果吗？ weboser 发表于 2022-9-30 00:38
这个再次初始化会带来什么后果吗？
比如此贴4楼的问题
https://www.armbbs.cn/forum.php?mod=viewthread&tid=115762 好家伙，就这个问题找了两天:'(
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