Windows 使用makefile和boot+app方式开发stm32h750
为啥论坛没法写md文档呢文档在这Budali11/stm32h7-bootloader-application: 在stm32h750上使用bootloader+Application开发 (github.com) 谢谢楼主分享，整理的非常好，论坛不支持Markdown openocd是怎么获取到外部qspi-flash的信息的？我按照步骤修改好了stm32h7x.cfg文件，用telnet打开openocd创建的端口查询当前的flash列表，列表有qspi-flash，但是查询信息出错。
Open On-Chip Debugger
> flash list
{name stm32h7x.bank1.cpu0 driver stm32h7x base 134217728 size 0 bus_width 0 chip_width 0 target stm32h7x.cpu0} {name stm32h7x.qspi driver stmqspi base 2415919104 size 0 bus_width 0 chip_width 0 target stm32h7x.cpu0}
> flash info 1
timeout
timeout
error retrieving flash info
#1 : stmqspi at 0x90000000, size 0x00000000, buswidth 0, chipwidth 0
QSPI flash bank not probed yet
> reset
> halt
target halted due to debug-request, current mode: Thread
xPSR: 0x81000000 pc: 0x08005e12 msp: 0x2001ffa8
> flash info 1
timeout
timeout
error retrieving flash info
#1 : stmqspi at 0x90000000, size 0x00000000, buswidth 0, chipwidth 0
QSPI flash bank not probed yet
>
另外，我用的是h750vb，qspi挂载在bank2，目前驱动正常能读写。 MD文档用什么软件打开看比较方便？ 浏览器除外，主要用于阅读本地文件哈，{:33:} morning_enr6U 发表于 2022-8-24 11:29
MD文档用什么软件打开看比较方便？ 浏览器除外，主要用于阅读本地文件哈，
notepad++可以显示md caicaptain2 发表于 2022-8-24 11:33
notepad++可以显示md
np++反华严重，已经弃用了！ 楼上的，有推荐的吗？ morning_enr6U 发表于 2022-8-24 11:29
MD文档用什么软件打开看比较方便？ 浏览器除外，主要用于阅读本地文件哈，
typora 关于makefile和openocd这两个东西，你们都是从哪里找到玩法的？
我从百度上搜索，都是一些零零散散的资料。
现在只会简单的修改，但是不清楚这两个东西的原理是什么。自己想改的复杂一点去哪里可以学？ morning_enr6U 发表于 2022-8-25 08:36
楼上的，有推荐的吗？
VSCODE，这些都支持。除了一个会自动覆盖内容的bug，其他都挺好。 记录一下使用mingw32+makefile命令行+daplink+openocd的方式烧录h750外部qspi-flash的后续：
1.目前openocd最新的版本（0.11.0 (2021-11-18)）已经对st的qspi有了很好的支持，具体可以看官方github上的stmqpsi.c的实现，并配合stm32h750b-disco.cfg和stm32h7x_dual_qspi.cfg这两个文件来看。
[https://github.com/sysprogs/openocd]附上我编改的.cfg配置文件
2.在stm32h7x_qspi.cfg中重点实现了io映射初始化和qpsi初始化，这部分配置要确保无误。
3.openocd的烧录命令可参考网上的一些方法，这里放出我在makefile上的命令作参考：
OCD_EXE = ./tools/OpenOCD/bin/openocd.exe
OCD_INF = ./tools/OpenOCD/scripts/interface/cmsis-dap.cfg
OCD_TARGET = ./tools/OpenOCD/scripts/target/stm32h7x.cfg
OCD_TARGET_QSPI = ./tools/OpenOCD/scripts/target/stm32h7x_qspi.cfg
flash:
$(OCD_EXE) -f $(OCD_INF) -c "transport select swd" -f $(OCD_TARGET) -c init -c halt -c "flash write_image erase $(FLASH_HEX)" -c reset -c shutdown
# $(OCD_EXE) -f $(OCD_INF) -c "transport select swd" -f $(OCD_TARGET) -c "init; halt; flash write_image erase $(FLASH_HEX); reset; shutdown;"
flash-qspi:
$(OCD_EXE) -f $(OCD_TARGET_QSPI) -c "init; reset init; halt;" -c "flash write_image erase ./testbin.bin 0x90000000" -c reset -c shutdown
4.实现原理：命令openocd.exe -f $(CFG)启动openocd后，再输入命令“reset init”即可启动stm32h7x_qspi.cfg文件中的初始化代码，从而MCU相应的外设得到了初始化，随后openocd调用自身的stmqspi部分代码进行flash的擦除与写入。
参考网址：
https://club.rt-thread.org/ask/article/95a03d2494e01ada.html
akatsuki_lim 发表于 2022-8-26 18:47
记录一下使用mingw32+makefile命令行+daplink+openocd的方式烧录h750外部qspi-flash的后续：
1.目前open ...
我靠！大佬！一开始我也遇到读不了flash信息的问题，不过后来我貌似是通过修改qspi部分的代码解决的。 morning_enr6U 发表于 2022-8-24 11:29
MD文档用什么软件打开看比较方便？ 浏览器除外，主要用于阅读本地文件哈，
我是用typora的，这个比较适合编辑吧。不过只用来看的话其他免费的也还行吧。 会飞的猪_2020 发表于 2022-8-25 09:51
关于makefile和openocd这两个东西，你们都是从哪里找到玩法的？
我从百度上搜索，都是一些零零散散的资料 ...
可以在官网找到参考手册的。
make：GNU make
openocd：openocd document 会飞的猪_2020 发表于 2022-8-25 09:51
关于makefile和openocd这两个东西，你们都是从哪里找到玩法的？
我从百度上搜索，都是一些零零散散的资料 ...
中文的阅读起来会方便一点
akatsuki_lim 发表于 2022-8-26 18:47
记录一下使用mingw32+makefile命令行+daplink+openocd的方式烧录h750外部qspi-flash的后续：
1.目前open ...
你好可以重新发一下这两个cfg文件吗 下载不了了 vs code 装MD插件就可以很方便的编写查看MD文件了 yuyike 发表于 2024-2-21 14:29
你好可以重新发一下这两个cfg文件吗 下载不了了
我把源码贴一下
stm32h7x_qspi.cfg:
# SPDX-License-Identifier: GPL-2.0-or-later
# This is a stm32h750b-dk with a single STM32H750XBH6 chip.
# www.st.com/en/product/stm32h750b-dk.html
#
# This is for using the onboard STLINK
source
# transport select hla_swd
# set CHIPNAME stm32h750vbt6
# enable stmqspi
if {!} {
set QUADSPI 1
}
source
# reset_config srst_only
# QUADSPI initialization
# qpi: 4-line mode
proc qspi_init { qpi } {
global a
mmw 0x580244E0 0x000007FF 0 ;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
mmw 0x580244D4 0x00004000 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock)
sleep 1 ;# Wait for clock startup
# QSPI BK2 IO
# QSPI_BK2_NCS: PC11/AF9, QSPI_CLK: PB2/AF9,
# QSPI_BK2_IO0: PE7/AF10, QSPI_BK2_IO1: PE8/AF10, QSPI_BK2_IO2: PE9/AF10, QSPI_BK2_IO3: PE10/AF10
# PB02:AF09:V, PC11:AF09:V, PE10:AF10:V, PE09:AF10:V, PE08:AF10:V, PE07:AF10:V
# Port B: PB02:AF09:V
mmw 0x58020400 0x00000020 0x00000010 ;# MODER
mmw 0x58020408 0x00000030 0x00000000 ;# OSPEEDR
mmw 0x5802040C 0x00000000 0x00000030 ;# PUPDR
mmw 0x58020420 0x00000900 0x00000600 ;# AFRL
# Port C: PC11:AF09:V
mmw 0x58020800 0x00800000 0x00400000 ;# MODER
mmw 0x58020808 0x00C00000 0x00000000 ;# OSPEEDR
mmw 0x5802080C 0x00000000 0x00C00000 ;# PUPDR
mmw 0x58020824 0x00009000 0x00006000 ;# AFRH
# Port E: PE10:AF10:V, PE09:AF10:V, PE08:AF10:V, PE07:AF10:V
mmw 0x58021000 0x002A8000 0x00154000 ;# MODER
mmw 0x58021008 0x003FC000 0x00000000 ;# OSPEEDR
mmw 0x5802100C 0x00000000 0x003FC000 ;# PUPDR
mmw 0x58021020 0xA0000000 0x50000000 ;# AFRL
mmw 0x58021024 0x00000AAA 0x00000555 ;# AFRH
# Port D: 14 15 for led
mmw 0x58020C00 0x50000000 0xA0000000 ;# MODER
mmw 0x58020C04 0x00000000 0x00000000 ;# OTYPER
mmw 0x58020C08 0x50000000 0xA0000000 ;# OSPEEDR
mmw 0x58020C0C 0x50000000 0xA0000000 ;# PUPDR
mmw 0x58020C14 0x00000000 0x00000000 ;# ODR
sleep 1
# correct FSIZE is 0x16, however, this causes trouble when
# reading the last bytes at end of bank in *memory mapped* mode
# for quad flash mode w25q64jv
mww 0x52005000 0x01000390 ;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1
mww 0x52005004 0x00160200 ;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x02, CKMODE=0
mww 0x52005030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
mww 0x52005014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1
mmw 0x52005000 0x00000001 0 ;# QUADSPI_CR: EN=1
# Exit QPI mode
# mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
# mww 0x52005014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI
# sleep 1
if { $qpi == 1 } {
# Write Enable
# mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
# mww 0x52005014 0x00000106 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
# sleep 1
# # Configure dummy clocks via volatile configuration register
# mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
# mww 0x52005010 0x00000001 ;# QUADSPI_DLR: 2 data bytes
# mww 0x52005014 0x01000181 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.
# mwh 0x52005020 0xABAB ;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks
# sleep 1
# # Write Enable
# mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
# mww 0x52005014 0x00000106 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
# sleep 1
# # Enable QPI mode via enhanced volatile configuration register
# mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
# mww 0x52005010 0x00000001 ;# QUADSPI_DLR: 2 data bytes
# mww 0x52005014 0x01000161 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg.
# mwh 0x52005020 0x3F3F ;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode
# sleep 1
# # Enter QPI mode
# mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
# mww 0x52005014 0x00000135 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI
# sleep 1
# # memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only)
# mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
# mww 0x52005014 0x0F283FEC ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ
} else {
# memory-mapped read mode with 4-byte addresses
# mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
# mww 0x52005014 0x0D003513 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
}
}
$_CHIPNAME.cpu0 configure -event reset-init {
global QUADSPI
# mmw 0x52002000 0x00000004 0x0000000B ;# FLASH_ACR: 4 WS for 192 MHZ HCLK
# mmw 0x58024400 0x00000001 0x00000018 ;# RCC_CR: HSIDIV=1, HSI on
# mmw 0x58024410 0x10000000 0xEE000007 ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
# mww 0x58024418 0x00000040 ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
# mww 0x5802441C 0x00000440 ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
# mww 0x58024420 0x00000040 ;# RCC_D3CFGR: D3PPRE=2
# mww 0x58024428 0x00000040 ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
# mmw 0x5802442C 0x0001000C 0x00000002 ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
# mww 0x58024430 0x01070217 ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
# mmw 0x58024400 0x01000000 0 ;# RCC_CR: PLL1ON=1
# sleep 1
# mmw 0x58024410 0x00000003 0 ;# RCC_CFGR: PLL1 as system clock
# sleep 1
# adapter speed 24000
if { $QUADSPI } {
qspi_init 1
}
}
stm32h7x.cfg
# script for stm32h7x family
#
# stm32h7 devices support both JTAG and SWD transports.
#
source
source
if { } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME stm32h7x
}
if { } {
set $_CHIPNAME.DUAL_BANK $DUAL_BANK
unset DUAL_BANK
} else {
set $_CHIPNAME.DUAL_BANK 0
}
if { } {
set $_CHIPNAME.DUAL_CORE $DUAL_CORE
unset DUAL_CORE
} else {
set $_CHIPNAME.DUAL_CORE 0
}
# Issue a warning when hla is used, and fallback to single core configuration
if { && } {
echo "Warning : hla does not support multicore debugging"
set $_CHIPNAME.DUAL_CORE 0
}
if { } {
set $_CHIPNAME.USE_CTI $USE_CTI
unset USE_CTI
} else {
set $_CHIPNAME.USE_CTI 0
}
# Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0
if { ! && } {
echo "Warning : could not use CTI with a single core device, CTI is disabled"
set $_CHIPNAME.USE_CTI 0
}
set _ENDIAN little
# Work-area is a space in RAM used for flash programming
# By default use 64kB
if { } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x10000
}
#jtag scan chain
if { } {
set _CPUTAPID $CPUTAPID
} else {
if { } {
set _CPUTAPID 0x6ba00477
} {
set _CPUTAPID 0x6ba02477
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if {} {
jtag newtap $_CHIPNAME bs -irlen 5
}
if {!} {
# STM32H7 provides an APB-AP at access port 2, which allows the access to
# the debug and trace features on the system APB System Debug Bus (APB-D).
target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
swocreate $_CHIPNAME.swo-dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000
tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000
}
target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
$_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
if {} {
flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0
}
if {} {
target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3
$_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1
if {} {
flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1
}
}
# Make sure that cpu0 is selected
targets $_CHIPNAME.cpu0
if { && $QUADSPI } {
set a ]
set _QSPINAME $_CHIPNAME.qspi
flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
} else {
if { && $OCTOSPI1 } {
set a ]
set _OCTOSPINAME1 $_CHIPNAME.octospi1
flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
}
if { && $OCTOSPI2 } {
set b ]
set _OCTOSPINAME2 $_CHIPNAME.octospi2
flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000
}
}
# Clock after reset is HSI at 64 MHz, no need of PLL
adapter speed 1800
adapter srst delay 100
if {} {
jtag_ntrst_delay 100
}
# use hardware reset
#
# The STM32H7 does not support connect_assert_srst mode because the AXI is
# unavailable while SRST is asserted, and that is used to access the DBGMCU
# component at 0x5C001000 in the examine-end event handler.
#
# It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
# of the default AP0, and that works with SRST asserted; however, nonzero AP
# usage does not work with HLA, so is not done by default. That change could be
# made in a local configuration file if connect_assert_srst mode is needed for
# a specific application and a non-HLA adapter is in use.
reset_config srst_nogate
if {!} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
if {} {
$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
}
# Set CSW, which according to ARM ADI v5 appendix E1.4 maps to AHB signal
# HPROT, which according to AMBA AHB/ASB/APB specification chapter 3.7.3
# makes the data access cacheable. This allows reading and writing data in the
# CPU cache from the debugger, which is far more useful than going straight to
# RAM when operating on typical variables, and is generally no worse when
# operating on special memory locations.
$_CHIPNAME.dap apcsw 0x08000000 0x08000000
}
$_CHIPNAME.cpu0 configure -event examine-end {
# Enable D3 and D1 DBG clocks
# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain
stm32h7x_dbgmcu_mmw 0x004 0x00000007 0
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain
stm32h7x_dbgmcu_mmw 0x004 0x00000038 0
# Stop watchdog counters during halt
# DBGMCU_APB3FZ1 |= WWDG1
stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
# DBGMCU_APB1LFZ1 |= WWDG2
stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
# DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
# Enable clock for tracing
# DBGMCU_CR |= TRACECLKEN
stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
# RM0399 (id 0x450) M7+M4 with SWO Funnel
# RM0433 (id 0x450) M7 with SWO Funnel
# RM0455 (id 0x480) M7 without SWO Funnel
# RM0468 (id 0x483) M7 without SWO Funnel
# Enable CM7 and CM4 slave ports in SWO trace Funnel
# Works ok also on devices single core and without SWO funnel
# Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF
# SWTF_CTRL |= ENS0 | ENS1
stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0
}
$_CHIPNAME.cpu0 configure -event reset-init {
# Clock after reset is HSI at 64 MHz, no need of PLL
adapter speed 4000
}
# get _CHIPNAME from current target
proc stm32h7x_get_chipname {} {
set t
set sep
if {$sep == -1} {
return $t
}
return ]
}
if {} {
$_CHIPNAME.cpu1 configure -event examine-end {
set _CHIPNAME
global $_CHIPNAME.USE_CTI
# Stop watchdog counters during halt
# DBGMCU_APB3FZ2 |= WWDG1
stm32h7x_dbgmcu_mmw 0x038 0x00000040 0
# DBGMCU_APB1LFZ2 |= WWDG2
stm32h7x_dbgmcu_mmw 0x040 0x00000800 0
# DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2
stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0
if {} {
stm32h7x_cti_start
}
}
}
# like mrw, but with target selection
proc stm32h7x_mrw {used_target reg} {
set value ""
$used_target mem2array value 32 $reg 1
return $value(0)
}
# like mmw, but with target selection
proc stm32h7x_mmw {used_target reg setbits clearbits} {
set old
set new
$used_target mww $reg $new
}
# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
# this procedure will use the mem_ap on AP2 whenever possible
proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
# use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
if {!} {
set _CHIPNAME
set used_target $_CHIPNAME.ap2
set reg_addr
} {
set used_target
set reg_addr
}
stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
}
if {} {
# create CTI instances for both cores
cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0043000
cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xE0043000
$_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
$_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
$_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
$_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
proc stm32h7x_cti_start {} {
set _CHIPNAME
# Configure Cores' CTIs to halt each other
# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
$_CHIPNAME.cti0 write INEN0 0x1
$_CHIPNAME.cti0 write OUTEN0 0x1
$_CHIPNAME.cti1 write INEN0 0x1
$_CHIPNAME.cti1 write OUTEN0 0x1
# enable CTIs
$_CHIPNAME.cti0 enable on
$_CHIPNAME.cti1 enable on
}
proc stm32h7x_cti_stop {} {
set _CHIPNAME
$_CHIPNAME.cti0 enable off
$_CHIPNAME.cti1 enable off
}
proc stm32h7x_cti_prepare_restart_all {} {
stm32h7x_cti_prepare_restart cti0
stm32h7x_cti_prepare_restart cti1
}
proc stm32h7x_cti_prepare_restart {cti} {
set _CHIPNAME
# Acknowlodge EDBGRQ at TRIGOUT0
$_CHIPNAME.$cti write INACK 0x01
$_CHIPNAME.$cti write INACK 0x00
}
}
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