STM32F249+LAN8720A 内网TCP反而不如外网中转
系列问题前情提要:
STM32F429+LAN8720A 部分老式交换机网口灯不亮
千兆交换机LAN8720A手动协商只能到10M
目前情况:STM32F429+LAN8742成功让测试环境和生产环境自动协商到100M全双工。
但是出现新的情况了,测试环境100M全双工下通过TCP上传EMMC中文件到服务器能达到3MB/s,生产环境也是100M全双工但是速度低到0.15MB/s
要知道之前STM32F249+LAN8720A之前生产环境只能手动协商到10M的情况下这个上传速度也在0.8MB/s,换了LAN8742到100M反而速度降低了,程序未进行改动。
然后各种排查,整理如下:
序号
芯片 环境网络
设备请求到服务器路径
结果
1
LAN8720A 测试环境自动协商 100M全双工
内网不同网段
3.2MB/s
2
LAN8720A 生产环境手动协商 10M全双工内网不同网段
0.8MB/s
3
LAN8742
测试环境自动协商 100M全双工内网不同网段
3.2MB/s
4
LAN8742生产环境自动协商 100M全双工内网不同网段0.15MB/s
5
LAN8742
测试环境自动协商 100M全双工将服务端口穿透到阿里云服务器端口
1.5MB/s
6
LAN8742
生产环境自动协商 100M全双工将服务端口内网穿透到阿里云服务器端口
1.5MB/s
5和6的1.5MB/s应该是受限于阿里云服务器。
通过4和6的结果比对 是不是能看出是在生产环境 设备到服务器之间 TCP传输有问题?
我用的
#define MEM_SIZE (1024 * 20)
#define TCP_MSS 1460
#define TCP_SND_BUF TCP_MSS*12
lwip其他配置没做大的改动
程序里面是
while(文件未结束) {
uint32_t size = tcp_sndbuf();
while(size==0){
size = tcp_sndbuf();
}
// 文件中读取size大小内容
f_read(size_buf);
// 发送tcp_write
tcp_write(tcp_buf);
}
生产环境实际是1000M的,测试都没问题的,也问过对方网管,内网之间未做限制。
现在就是奇怪第4组这个生产环境实际操作才0.15MB/s?内网之间传输反而不如阿里云服务器走外网再中转一层
大佬有没有什么思路?
寄存器有些区别
8720
/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------
*
* $Date: 25. May 2018
* $Revision: V6.2
*
* Project: Ethernet Physical Layer Transceiver (PHY)
* Definitions for LAN8720
* -------------------------------------------------------------------- */
#ifndef __PHY_LAN8720_H
#define __PHY_LAN8720_H
#include "Driver_ETH_PHY.h"
/* Basic Registers */
#define REG_BMCR 0x00 /* Basic Mode Control Register */
#define REG_BMSR 0x01 /* Basic Mode Status Register */
#define REG_PHYIDR1 0x02 /* PHY Identifier 1 */
#define REG_PHYIDR2 0x03 /* PHY Identifier 2 */
#define REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
#define REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Ability */
#define REG_ANER 0x06 /* Auto-Neg. Expansion Register */
/* LAN8720 PHY Extended Registers */
#define REG_MCSR 0x11 /* Mode Control/Status Register */
#define REG_SR 0x12 /* Special Modes Register */
#define REG_SECR 0x1A /* Syytem Error Counter Register */
#define REG_CSIR 0x1B /* Control/Status Indication Register*/
#define REG_ISR 0x1D /* Interrupt Source Register */
#define REG_IMR 0x1E /* Interrupt Mask Register */
#define REG_PSCSR 0x1F /* PHY Special Ctrl/Status Register*/
/* Basic Mode Control Register */
#define BMCR_RESET 0x8000 /* Software Reset */
#define BMCR_LOOPBACK 0x4000 /* Loopback mode */
#define BMCR_SPEED_SEL 0x2000 /* Speed Select (1=100Mb/s) */
#define BMCR_ANEG_EN 0x1000 /* Auto Negotiation Enable */
#define BMCR_POWER_DOWN 0x0800 /* LAN8700 Power Down */
#define BMCR_ISOLATE 0x0400 /* Isolate Media interface */
#define BMCR_REST_ANEG 0x0200 /* Restart Auto Negotiation */
#define BMCR_DUPLEX 0x0100 /* Duplex Mode (1=Full duplex) */
#define BMCR_COL_TEST 0x0080 /* Enable Collision Test */
/* Basic Status Register */
#define BMSR_100B_T4 0x8000 /* 100BASE-T4 Capable */
#define BMSR_100B_TX_FD 0x4000 /* 100BASE-TX Full Duplex Capable */
#define BMSR_100B_TX_HD 0x2000 /* 100BASE-TX Half Duplex Capable */
#define BMSR_10B_T_FD 0x1000 /* 10BASE-T Full Duplex Capable */
#define BMSR_10B_T_HD 0x0800 /* 10BASE-T Half Duplex Capable */
#define BMSR_ANEG_COMPL 0x0020 /* Auto Negotiation Complete */
#define BMSR_REM_FAULT 0x0010 /* Remote Fault */
#define BMSR_ANEG_ABIL 0x0008 /* Auto Negotiation Ability */
#define BMSR_LINK_STAT 0x0004 /* Link Status (1=established) */
#define BMSR_JABBER_DET 0x0002 /* Jaber Detect */
#define BMSR_EXT_CAPAB 0x0001 /* Extended Capability */
/* PHY Identifier Registers */
#define PHY_ID1 0x0007 /* LAN8720 Device Identifier MSB */
#define PHY_ID2 0xC0F0 /* LAN8720 Device Identifier LSB */
/* PHY Special Control/Status Register */
#define PSCSR_AUTODONE 0x1000 /* Auto-negotiation is done */
#define PSCSR_DUPLEX 0x0010 /* Duplex Status (1=Full duplex) */
#define PSCSR_SPEED 0x0004 /* Speed10 Status (1=10MBit/s) */
/* PHY Driver State Flags */
#define PHY_INIT 0x01U /* Driver initialized */
#define PHY_POWER 0x02U /* Driver power is on */
/* PHY Driver Control Structure */
typedef struct phy_ctrl {
ARM_ETH_PHY_Read_treg_rd; /* PHY register read function */
ARM_ETH_PHY_Write_t reg_wr; /* PHY register write function */
uint16_t bmcr; /* BMCR register value */
uint8_t flags; /* Control flags */
uint8_t rsvd; /* Reserved */
} PHY_CTRL;
#endif /* __PHY_LAN8720_H */
8742
/*
* Copyright (c) 2013-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------
*
* $Date: 6. May 2019
* $Revision: V1.3
*
* Project: Ethernet Physical Layer Transceiver (PHY)
* Definitions for LAN8742A
* -------------------------------------------------------------------- */
#ifndef __PHY_LAN8742A_H
#define __PHY_LAN8742A_H
#include "Driver_ETH_PHY.h"
/* Basic Registers */
#define REG_BCR 0 /* Basic Control Register */
#define REG_BSR 1 /* Basic Status Register */
/* Extended Registers */
#define REG_PHYIDR1 2 /* PHY Identifier 1 */
#define REG_PHYIDR2 3 /* PHY Identifier 2 */
#define REG_ANAR 4 /* Auto-Negotiation Advertisement */
#define REG_ANLPAR 5 /* Auto-Neg. Link Partner Ability */
#define REG_ANER 6 /* Auto-Neg. Expansion Register */
#define REG_ANEG_NP_TX 7 /* Auto-Neg. Next Page Tx */
#define REG_ANEG_NP_RX 8 /* Auto-Neg. Next Page Rx */
#define REG_MMD_ACCES_CTRL13 /* MMD Access Control */
#define REG_MMD_ACCES_AD 14 /* MMD Access Address/Data */
/* Vendor-specific Registers */
#define REG_MCSR 17 /* Mode Control/Status Register */
#define REG_SPEC_MODE 18 /* Special Modes Register */
#define REG_TDR_PAT_DEL 24 /* TDR Patterns/Delay Control Reg. */
#define REG_TDR_CTRL_STAT 25 /* TDR Control/Status Register */
#define REG_SEC 26 /* System Error Counter Register */
#define REG_SC_SI 27 /* Specifal Control/Status Indication*/
#define REG_CABLE_LEN 28 /* Cable Length Register */
#define REG_ISF 29 /* Interrupt Source Flag Register */
#define REG_IM 30 /* Interrupt Mask Register */
#define REG_PSCS 31 /* PHY Special Ctrl/Status Register*/
/* Basic Control Register */
#define BCR_RESET 0x8000 /* Software Reset */
#define BCR_LOOPBACK 0x4000 /* Loopback mode */
#define BCR_SPEED_SEL 0x2000 /* Speed Select (1=100Mb/s) */
#define BCR_ANEG_EN 0x1000 /* Auto Negotiation Enable */
#define BCR_POWER_DOWN 0x0800 /* Power Down (1=power down mode) */
#define BCR_ISOLATE 0x0400 /* Isolate Media interface */
#define BCR_REST_ANEG 0x0200 /* Restart Auto Negotiation */
#define BCR_DUPLEX 0x0100 /* Duplex Mode (1=Full duplex) */
#define BCR_COL_TEST 0x0080 /* Enable Collision Test */
/* Basic Status Register */
#define BSR_100B_T4 0x8000 /* 100BASE-T4 Capable */
#define BSR_100B_TX_FD 0x4000 /* 100BASE-TX Full Duplex Capable */
#define BSR_100B_TX_HD 0x2000 /* 100BASE-TX Half Duplex Capable */
#define BSR_10B_T_FD 0x1000 /* 10BASE-T Full Duplex Capable */
#define BSR_10B_T_HD 0x0800 /* 10BASE-T Half Duplex Capable */
#define BSR_100B_T2_FD 0x0400 /* 1000BASE-T2 Full Duplex Capable */
#define BSR_100B_T2_HD 0x0200 /* 1000BASE-T2 Half Duplex Capable */
#define BSR_EXTENDED_STAT 0x0100 /* Extended Status in register 15 */
#define BSR_ANEG_COMPL 0x0020 /* Auto Negotiation Complete */
#define BSR_REM_FAULT 0x0010 /* Remote Fault */
#define BSR_ANEG_ABIL 0x0008 /* Auto Negotiation Ability */
#define BSR_LINK_STAT 0x0004 /* Link Status (1=link us up) */
#define BSR_JABBER_DET 0x0002 /* Jabber Detect */
#define BSR_EXT_CAPAB 0x0001 /* Extended Capabilities */
/* PHY Identifier Registers */
#define PHY_ID1 0x0007 /* LAN8742A Device Identifier MSB */
#define PHY_ID2 0xC130 /* LAN8742A Device Identifier LSB */
/* PHY Special Control/Status Register */
#define PSCS_AUTODONE 0x1000 /* Auto-negotiation is done */
#define PSCS_DUPLEX 0x0010 /* Duplex Status (1=Full duplex) */
#define PSCS_SPEED 0x0004 /* Speed10 Status (1=10MBit/s) */
/* PHY Driver State Flags */
#define PHY_INIT 0x01U /* Driver initialized */
#define PHY_POWER 0x02U /* Driver power is on */
/* PHY Driver Control Structure */
typedef struct phy_ctrl {
ARM_ETH_PHY_Read_treg_rd; /* PHY register read function */
ARM_ETH_PHY_Write_t reg_wr; /* PHY register write function */
uint16_t bcr; /* BCR register value */
uint8_t flags; /* Control flags */
uint8_t rsvd; /* Reserved */
} PHY_CTRL;
#endif /* __PHY_LAN8742A_H */
eric2013 发表于 2024-3-19 07:46
寄存器有些区别
8720
我一直要的cubemx生成的这个
/**
******************************************************************************
* @file lan8742.h
* @authorMCD Application Team
* @brief This file contains all the functions prototypes for the
* lan8742.c PHY driver.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LAN8742_H
#define LAN8742_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Component
* @{
*/
/** @defgroup LAN8742
* @{
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup LAN8742_Exported_Constants LAN8742 Exported Constants
* @{
*/
/** @defgroup LAN8742_Registers_Mapping LAN8742 Registers Mapping
* @{
*/
#define LAN8742_BCR ((uint16_t)0x0000U)
#define LAN8742_BSR ((uint16_t)0x0001U)
#define LAN8742_PHYI1R ((uint16_t)0x0002U)
#define LAN8742_PHYI2R ((uint16_t)0x0003U)
#define LAN8742_ANAR ((uint16_t)0x0004U)
#define LAN8742_ANLPAR ((uint16_t)0x0005U)
#define LAN8742_ANER ((uint16_t)0x0006U)
#define LAN8742_ANNPTR ((uint16_t)0x0007U)
#define LAN8742_ANNPRR ((uint16_t)0x0008U)
#define LAN8742_MMDACR ((uint16_t)0x000DU)
#define LAN8742_MMDAADR((uint16_t)0x000EU)
#define LAN8742_ENCTR ((uint16_t)0x0010U)
#define LAN8742_MCSR ((uint16_t)0x0011U)
#define LAN8742_SMR ((uint16_t)0x0012U)
#define LAN8742_TPDCR ((uint16_t)0x0018U)
#define LAN8742_TCSR ((uint16_t)0x0019U)
#define LAN8742_SECR ((uint16_t)0x001AU)
#define LAN8742_SCSIR ((uint16_t)0x001BU)
#define LAN8742_CLR ((uint16_t)0x001CU)
#define LAN8742_ISFR ((uint16_t)0x001DU)
#define LAN8742_IMR ((uint16_t)0x001EU)
#define LAN8742_PHYSCSR((uint16_t)0x001FU)
/**
* @}
*/
/** @defgroup LAN8742_BCR_Bit_Definition LAN8742 BCR Bit Definition
* @{
*/
#define LAN8742_BCR_SOFT_RESET ((uint16_t)0x8000U)
#define LAN8742_BCR_LOOPBACK ((uint16_t)0x4000U)
#define LAN8742_BCR_SPEED_SELECT ((uint16_t)0x2000U)
#define LAN8742_BCR_AUTONEGO_EN ((uint16_t)0x1000U)
#define LAN8742_BCR_POWER_DOWN ((uint16_t)0x0800U)
#define LAN8742_BCR_ISOLATE ((uint16_t)0x0400U)
#define LAN8742_BCR_RESTART_AUTONEGO ((uint16_t)0x0200U)
#define LAN8742_BCR_DUPLEX_MODE ((uint16_t)0x0100U)
/**
* @}
*/
/** @defgroup LAN8742_BSR_Bit_Definition LAN8742 BSR Bit Definition
* @{
*/
#define LAN8742_BSR_100BASE_T4 ((uint16_t)0x8000U)
#define LAN8742_BSR_100BASE_TX_FD ((uint16_t)0x4000U)
#define LAN8742_BSR_100BASE_TX_HD ((uint16_t)0x2000U)
#define LAN8742_BSR_10BASE_T_FD ((uint16_t)0x1000U)
#define LAN8742_BSR_10BASE_T_HD ((uint16_t)0x0800U)
#define LAN8742_BSR_100BASE_T2_FD ((uint16_t)0x0400U)
#define LAN8742_BSR_100BASE_T2_HD ((uint16_t)0x0200U)
#define LAN8742_BSR_EXTENDED_STATUS((uint16_t)0x0100U)
#define LAN8742_BSR_AUTONEGO_CPLT ((uint16_t)0x0020U)
#define LAN8742_BSR_REMOTE_FAULT ((uint16_t)0x0010U)
#define LAN8742_BSR_AUTONEGO_ABILITY ((uint16_t)0x0008U)
#define LAN8742_BSR_LINK_STATUS ((uint16_t)0x0004U)
#define LAN8742_BSR_JABBER_DETECT ((uint16_t)0x0002U)
#define LAN8742_BSR_EXTENDED_CAP ((uint16_t)0x0001U)
/**
* @}
*/
/** @defgroup LAN8742_PHYI1R_Bit_Definition LAN8742 PHYI1R Bit Definition
* @{
*/
#define LAN8742_PHYI1R_OUI_3_18 ((uint16_t)0xFFFFU)
/**
* @}
*/
/** @defgroup LAN8742_PHYI2R_Bit_Definition LAN8742 PHYI2R Bit Definition
* @{
*/
#define LAN8742_PHYI2R_OUI_19_24 ((uint16_t)0xFC00U)
#define LAN8742_PHYI2R_MODEL_NBR ((uint16_t)0x03F0U)
#define LAN8742_PHYI2R_REVISION_NBR ((uint16_t)0x000FU)
/**
* @}
*/
/** @defgroup LAN8742_ANAR_Bit_Definition LAN8742 ANAR Bit Definition
* @{
*/
#define LAN8742_ANAR_NEXT_PAGE ((uint16_t)0x8000U)
#define LAN8742_ANAR_REMOTE_FAULT ((uint16_t)0x2000U)
#define LAN8742_ANAR_PAUSE_OPERATION ((uint16_t)0x0C00U)
#define LAN8742_ANAR_PO_NOPAUSE ((uint16_t)0x0000U)
#define LAN8742_ANAR_PO_SYMMETRIC_PAUSE ((uint16_t)0x0400U)
#define LAN8742_ANAR_PO_ASYMMETRIC_PAUSE ((uint16_t)0x0800U)
#define LAN8742_ANAR_PO_ADVERTISE_SUPPORT ((uint16_t)0x0C00U)
#define LAN8742_ANAR_100BASE_TX_FD ((uint16_t)0x0100U)
#define LAN8742_ANAR_100BASE_TX ((uint16_t)0x0080U)
#define LAN8742_ANAR_10BASE_T_FD ((uint16_t)0x0040U)
#define LAN8742_ANAR_10BASE_T ((uint16_t)0x0020U)
#define LAN8742_ANAR_SELECTOR_FIELD ((uint16_t)0x000FU)
/**
* @}
*/
/** @defgroup LAN8742_ANLPAR_Bit_Definition LAN8742 ANLPAR Bit Definition
* @{
*/
#define LAN8742_ANLPAR_NEXT_PAGE ((uint16_t)0x8000U)
#define LAN8742_ANLPAR_REMOTE_FAULT ((uint16_t)0x2000U)
#define LAN8742_ANLPAR_PAUSE_OPERATION ((uint16_t)0x0C00U)
#define LAN8742_ANLPAR_PO_NOPAUSE ((uint16_t)0x0000U)
#define LAN8742_ANLPAR_PO_SYMMETRIC_PAUSE ((uint16_t)0x0400U)
#define LAN8742_ANLPAR_PO_ASYMMETRIC_PAUSE((uint16_t)0x0800U)
#define LAN8742_ANLPAR_PO_ADVERTISE_SUPPORT ((uint16_t)0x0C00U)
#define LAN8742_ANLPAR_100BASE_TX_FD ((uint16_t)0x0100U)
#define LAN8742_ANLPAR_100BASE_TX ((uint16_t)0x0080U)
#define LAN8742_ANLPAR_10BASE_T_FD ((uint16_t)0x0040U)
#define LAN8742_ANLPAR_10BASE_T ((uint16_t)0x0020U)
#define LAN8742_ANLPAR_SELECTOR_FIELD ((uint16_t)0x000FU)
/**
* @}
*/
/** @defgroup LAN8742_ANER_Bit_Definition LAN8742 ANER Bit Definition
* @{
*/
#define LAN8742_ANER_RX_NP_LOCATION_ABLE ((uint16_t)0x0040U)
#define LAN8742_ANER_RX_NP_STORAGE_LOCATION ((uint16_t)0x0020U)
#define LAN8742_ANER_PARALLEL_DETECT_FAULT((uint16_t)0x0010U)
#define LAN8742_ANER_LP_NP_ABLE ((uint16_t)0x0008U)
#define LAN8742_ANER_NP_ABLE ((uint16_t)0x0004U)
#define LAN8742_ANER_PAGE_RECEIVED ((uint16_t)0x0002U)
#define LAN8742_ANER_LP_AUTONEG_ABLE ((uint16_t)0x0001U)
/**
* @}
*/
/** @defgroup LAN8742_ANNPTR_Bit_Definition LAN8742 ANNPTR Bit Definition
* @{
*/
#define LAN8742_ANNPTR_NEXT_PAGE ((uint16_t)0x8000U)
#define LAN8742_ANNPTR_MESSAGE_PAGE ((uint16_t)0x2000U)
#define LAN8742_ANNPTR_ACK2 ((uint16_t)0x1000U)
#define LAN8742_ANNPTR_TOGGLE ((uint16_t)0x0800U)
#define LAN8742_ANNPTR_MESSAGGE_CODE ((uint16_t)0x07FFU)
/**
* @}
*/
/** @defgroup LAN8742_ANNPRR_Bit_Definition LAN8742 ANNPRR Bit Definition
* @{
*/
#define LAN8742_ANNPTR_NEXT_PAGE ((uint16_t)0x8000U)
#define LAN8742_ANNPRR_ACK ((uint16_t)0x4000U)
#define LAN8742_ANNPRR_MESSAGE_PAGE ((uint16_t)0x2000U)
#define LAN8742_ANNPRR_ACK2 ((uint16_t)0x1000U)
#define LAN8742_ANNPRR_TOGGLE ((uint16_t)0x0800U)
#define LAN8742_ANNPRR_MESSAGGE_CODE ((uint16_t)0x07FFU)
/**
* @}
*/
/** @defgroup LAN8742_MMDACR_Bit_Definition LAN8742 MMDACR Bit Definition
* @{
*/
#define LAN8742_MMDACR_MMD_FUNCTION ((uint16_t)0xC000U)
#define LAN8742_MMDACR_MMD_FUNCTION_ADDR((uint16_t)0x0000U)
#define LAN8742_MMDACR_MMD_FUNCTION_DATA((uint16_t)0x4000U)
#define LAN8742_MMDACR_MMD_DEV_ADDR ((uint16_t)0x001FU)
/**
* @}
*/
/** @defgroup LAN8742_ENCTR_Bit_Definition LAN8742 ENCTR Bit Definition
* @{
*/
#define LAN8742_ENCTR_TX_ENABLE ((uint16_t)0x8000U)
#define LAN8742_ENCTR_TX_TIMER ((uint16_t)0x6000U)
#define LAN8742_ENCTR_TX_TIMER_1S ((uint16_t)0x0000U)
#define LAN8742_ENCTR_TX_TIMER_768MS ((uint16_t)0x2000U)
#define LAN8742_ENCTR_TX_TIMER_512MS ((uint16_t)0x4000U)
#define LAN8742_ENCTR_TX_TIMER_265MS ((uint16_t)0x6000U)
#define LAN8742_ENCTR_RX_ENABLE ((uint16_t)0x1000U)
#define LAN8742_ENCTR_RX_MAX_INTERVAL ((uint16_t)0x0C00U)
#define LAN8742_ENCTR_RX_MAX_INTERVAL_64MS((uint16_t)0x0000U)
#define LAN8742_ENCTR_RX_MAX_INTERVAL_256MS ((uint16_t)0x0400U)
#define LAN8742_ENCTR_RX_MAX_INTERVAL_512MS ((uint16_t)0x0800U)
#define LAN8742_ENCTR_RX_MAX_INTERVAL_1S ((uint16_t)0x0C00U)
#define LAN8742_ENCTR_EX_CROSS_OVER ((uint16_t)0x0002U)
#define LAN8742_ENCTR_EX_MANUAL_CROSS_OVER((uint16_t)0x0001U)
/**
* @}
*/
/** @defgroup LAN8742_MCSR_Bit_Definition LAN8742 MCSR Bit Definition
* @{
*/
#define LAN8742_MCSR_EDPWRDOWN ((uint16_t)0x2000U)
#define LAN8742_MCSR_FARLOOPBACK ((uint16_t)0x0200U)
#define LAN8742_MCSR_ALTINT ((uint16_t)0x0040U)
#define LAN8742_MCSR_ENERGYON ((uint16_t)0x0002U)
/**
* @}
*/
/** @defgroup LAN8742_SMR_Bit_Definition LAN8742 SMR Bit Definition
* @{
*/
#define LAN8742_SMR_MODE ((uint16_t)0x00E0U)
#define LAN8742_SMR_PHY_ADDR ((uint16_t)0x001FU)
/**
* @}
*/
/** @defgroup LAN8742_TPDCR_Bit_Definition LAN8742 TPDCR Bit Definition
* @{
*/
#define LAN8742_TPDCR_DELAY_IN ((uint16_t)0x8000U)
#define LAN8742_TPDCR_LINE_BREAK_COUNTER ((uint16_t)0x7000U)
#define LAN8742_TPDCR_PATTERN_HIGH ((uint16_t)0x0FC0U)
#define LAN8742_TPDCR_PATTERN_LOW ((uint16_t)0x003FU)
/**
* @}
*/
/** @defgroup LAN8742_TCSR_Bit_Definition LAN8742 TCSR Bit Definition
* @{
*/
#define LAN8742_TCSR_TDR_ENABLE ((uint16_t)0x8000U)
#define LAN8742_TCSR_TDR_AD_FILTER_ENABLE ((uint16_t)0x4000U)
#define LAN8742_TCSR_TDR_CH_CABLE_TYPE ((uint16_t)0x0600U)
#define LAN8742_TCSR_TDR_CH_CABLE_DEFAULT ((uint16_t)0x0000U)
#define LAN8742_TCSR_TDR_CH_CABLE_SHORTED ((uint16_t)0x0200U)
#define LAN8742_TCSR_TDR_CH_CABLE_OPEN ((uint16_t)0x0400U)
#define LAN8742_TCSR_TDR_CH_CABLE_MATCH ((uint16_t)0x0600U)
#define LAN8742_TCSR_TDR_CH_STATUS ((uint16_t)0x0100U)
#define LAN8742_TCSR_TDR_CH_LENGTH ((uint16_t)0x00FFU)
/**
* @}
*/
/** @defgroup LAN8742_SCSIR_Bit_Definition LAN8742 SCSIR Bit Definition
* @{
*/
#define LAN8742_SCSIR_AUTO_MDIX_ENABLE ((uint16_t)0x8000U)
#define LAN8742_SCSIR_CHANNEL_SELECT ((uint16_t)0x2000U)
#define LAN8742_SCSIR_SQE_DISABLE ((uint16_t)0x0800U)
#define LAN8742_SCSIR_XPOLALITY ((uint16_t)0x0010U)
/**
* @}
*/
/** @defgroup LAN8742_CLR_Bit_Definition LAN8742 CLR Bit Definition
* @{
*/
#define LAN8742_CLR_CABLE_LENGTH ((uint16_t)0xF000U)
/**
* @}
*/
/** @defgroup LAN8742_IMR_ISFR_Bit_Definition LAN8742 IMR ISFR Bit Definition
* @{
*/
#define LAN8742_INT_8 ((uint16_t)0x0100U)
#define LAN8742_INT_7 ((uint16_t)0x0080U)
#define LAN8742_INT_6 ((uint16_t)0x0040U)
#define LAN8742_INT_5 ((uint16_t)0x0020U)
#define LAN8742_INT_4 ((uint16_t)0x0010U)
#define LAN8742_INT_3 ((uint16_t)0x0008U)
#define LAN8742_INT_2 ((uint16_t)0x0004U)
#define LAN8742_INT_1 ((uint16_t)0x0002U)
/**
* @}
*/
/** @defgroup LAN8742_PHYSCSR_Bit_Definition LAN8742 PHYSCSR Bit Definition
* @{
*/
#define LAN8742_PHYSCSR_AUTONEGO_DONE ((uint16_t)0x1000U)
#define LAN8742_PHYSCSR_HCDSPEEDMASK ((uint16_t)0x001CU)
#define LAN8742_PHYSCSR_10BT_HD ((uint16_t)0x0004U)
#define LAN8742_PHYSCSR_10BT_FD ((uint16_t)0x0014U)
#define LAN8742_PHYSCSR_100BTX_HD ((uint16_t)0x0008U)
#define LAN8742_PHYSCSR_100BTX_FD ((uint16_t)0x0018U)
/**
* @}
*/
/** @defgroup LAN8742_Status LAN8742 Status
* @{
*/
#defineLAN8742_STATUS_READ_ERROR ((int32_t)-5)
#defineLAN8742_STATUS_WRITE_ERROR ((int32_t)-4)
#defineLAN8742_STATUS_ADDRESS_ERROR ((int32_t)-3)
#defineLAN8742_STATUS_RESET_TIMEOUT ((int32_t)-2)
#defineLAN8742_STATUS_ERROR ((int32_t)-1)
#defineLAN8742_STATUS_OK ((int32_t) 0)
#defineLAN8742_STATUS_LINK_DOWN ((int32_t) 1)
#defineLAN8742_STATUS_100MBITS_FULLDUPLEX ((int32_t) 2)
#defineLAN8742_STATUS_100MBITS_HALFDUPLEX ((int32_t) 3)
#defineLAN8742_STATUS_10MBITS_FULLDUPLEX ((int32_t) 4)
#defineLAN8742_STATUS_10MBITS_HALFDUPLEX ((int32_t) 5)
#defineLAN8742_STATUS_AUTONEGO_NOTDONE ((int32_t) 6)
/**
* @}
*/
/** @defgroup LAN8742_IT_Flags LAN8742 IT Flags
* @{
*/
#defineLAN8742_WOL_IT LAN8742_INT_8
#defineLAN8742_ENERGYON_IT LAN8742_INT_7
#defineLAN8742_AUTONEGO_COMPLETE_IT LAN8742_INT_6
#defineLAN8742_REMOTE_FAULT_IT LAN8742_INT_5
#defineLAN8742_LINK_DOWN_IT LAN8742_INT_4
#defineLAN8742_AUTONEGO_LP_ACK_IT LAN8742_INT_3
#defineLAN8742_PARALLEL_DETECTION_FAULT_IT LAN8742_INT_2
#defineLAN8742_AUTONEGO_PAGE_RECEIVED_IT LAN8742_INT_1
/**
* @}
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup LAN8742_Exported_Types LAN8742 Exported Types
* @{
*/
typedef int32_t(*lan8742_Init_Func) (void);
typedef int32_t(*lan8742_DeInit_Func) (void);
typedef int32_t(*lan8742_ReadReg_Func) (uint32_t, uint32_t, uint32_t *);
typedef int32_t(*lan8742_WriteReg_Func)(uint32_t, uint32_t, uint32_t);
typedef int32_t(*lan8742_GetTick_Func)(void);
typedef struct
{
lan8742_Init_Func Init;
lan8742_DeInit_Func DeInit;
lan8742_WriteReg_FuncWriteReg;
lan8742_ReadReg_Func ReadReg;
lan8742_GetTick_Func GetTick;
} lan8742_IOCtx_t;
typedef struct
{
uint32_t DevAddr;
uint32_t Is_Initialized;
lan8742_IOCtx_t IO;
void *pData;
}lan8742_Object_t;
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LAN8742_Exported_Functions LAN8742 Exported Functions
* @{
*/
int32_t LAN8742_RegisterBusIO(lan8742_Object_t *pObj, lan8742_IOCtx_t *ioctx);
int32_t LAN8742_Init(lan8742_Object_t *pObj);
int32_t LAN8742_DeInit(lan8742_Object_t *pObj);
int32_t LAN8742_DisablePowerDownMode(lan8742_Object_t *pObj);
int32_t LAN8742_EnablePowerDownMode(lan8742_Object_t *pObj);
int32_t LAN8742_StartAutoNego(lan8742_Object_t *pObj);
int32_t LAN8742_GetLinkState(lan8742_Object_t *pObj);
int32_t LAN8742_SetLinkState(lan8742_Object_t *pObj, uint32_t LinkState);
int32_t LAN8742_EnableLoopbackMode(lan8742_Object_t *pObj);
int32_t LAN8742_DisableLoopbackMode(lan8742_Object_t *pObj);
int32_t LAN8742_EnableIT(lan8742_Object_t *pObj, uint32_t Interrupt);
int32_t LAN8742_DisableIT(lan8742_Object_t *pObj, uint32_t Interrupt);
int32_t LAN8742_ClearIT(lan8742_Object_t *pObj, uint32_t Interrupt);
int32_t LAN8742_GetITStatus(lan8742_Object_t *pObj, uint32_t Interrupt);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LAN8742_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
LinY 发表于 2024-3-19 09:34
我一直要的cubemx生成的这个
/**
******************************************* ...
有个地方可以改进下,修改RMII所设计到GPIO速度等级为low或者中等,测试下。 楼主问题解决了, eric2013 发表于 2024-3-19 07:46
寄存器有些区别
8720
感谢硬汉指导,这两个寄存器不一样啊,我以前有个板子8720缺货直接用的8742,没仔细看直接用了,幸亏没出现啥问题 还是没解决问题。头大。
LWIP有哪些参数可能会影响到传输的?
我刚开始以为是TCP_MSS用1460 会不会和其中哪个交换机配置冲突导致分页 然后传输变慢。
但是调低TCP_MSS之后试了速度还是那样 我在tcp_write之后跟着加上tcp_output 速度确实上去了
但是这种方式可行么?
我怕文件上传出问题。
LinY 发表于 2024-3-26 15:49
我在tcp_write之后跟着加上tcp_output 速度确实上去了
但是这种方式可行么?
我怕文件上传出问题。
可以考虑批量反复测试下,如果稳定,说明没问题了。 eric2013 发表于 2024-3-27 09:38
可以考虑批量反复测试下,如果稳定,说明没问题了。
本地内网测试有5%左右概率 文件校验不通过 LinY 发表于 2024-3-27 17:50
本地内网测试有5%左右概率 文件校验不通过
5%稍有点高。 感觉之间tcp_output 还是不太靠谱
想让lwip自己干这活
设置nodelay关闭Nagle算法也没效果
tcp_set_flags(pcb, TF_NODELAY);
目前优化了分包上传 加上了CRC校验
本来用软件CRC进行分包校验 总文件校验的
发现软件CRC太慢了 即便是用了小表查询的情况下
现在改成硬件CRC 但是硬件CRC只能做总文件的校验了
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