优化完善USB2.0高速版DAPLINK的一些细节设置

eric2013

引脚：

1. Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
   
2. and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
   
3. interface of a device. The following I/O Pins are provided:
   
4. 
   
5. JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
   
6. ---------------------------- | -------------------- | ---------------------------------------------
   
7. TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
   
8. TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
   
9. TDI: Test Data Input         |                      | Output Push/Pull
   
10. TDO: Test Data Output        |                      | Input            
    
11. nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
    
12. nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
    
13. 
    
14. 
    
15. DAP Hardware I/O Pin Access Functions
    
16. -------------------------------------
    
17. The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
    
18. these I/O Pins.
    
19. 
    
20. For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
    
21. This functions are provided to achieve faster I/O that is possible with some advanced GPIO
    
22. peripherals that can independently write/read a single I/O pin without affecting any other pins
    
23. of the same I/O port. The following SWDIO I/O Pin functions are provided:
    
24. - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
    
25. - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
    
26. - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
    
27. - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
    
28. */

复制代码

eric2013

1. /**
   
2. * @file    DAP_config.h
   
3. * @brief
   
4. *
   
5. * DAPLink Interface Firmware
   
6. * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
   
7. * SPDX-License-Identifier: Apache-2.0
   
8. *
   
9. * Licensed under the Apache License, Version 2.0 (the "License"); you may
   
10. * not use this file except in compliance with the License.
    
11. * You may obtain a copy of the License at
    
12. *
    
13. * http://www.apache.org/licenses/LICENSE-2.0
    
14. *
    
15. * Unless required by applicable law or agreed to in writing, software
    
16. * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
    
17. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    
18. * See the License for the specific language governing permissions and
    
19. * limitations under the License.
    
20. */
    
21. 
    
22. #ifndef __DAP_CONFIG_H__
    
23. #define __DAP_CONFIG_H__
    
24. 
    
25. #include "stm32f1xx.h"
    
26. #include "stdint.h"
    
27. #include "cmsis_os2.h"
    
28. #include "IO_Config.h"
    
29. #include "uart.h"
    
30. //#include "debug_cm.h"
    
31. //#include "swd_host.h"
    
32. //**************************************************************************************************
    
33. /**
    
34. \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
    
35. \ingroup DAP_ConfigIO_gr
    
36. @{
    
37. Provides definitions about:
    
38. - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
    
39. - Debug Unit communication packet size.
    
40. - Debug Access Port communication mode (JTAG or SWD).
    
41. - Optional information about a connected Target Device (for Evaluation Boards).
    
42. */
    
43. 
    
44. /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
    
45. /// This value is used to calculate the SWD/JTAG clock speed.
    
46. #define CPU_CLOCK               SystemCoreClock        ///< Specifies the CPU Clock in Hz
    
47. 
    
48. /// Number of processor cycles for I/O Port write operations.
    
49. /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
    
50. /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
    
51. /// requrie 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
    
52. /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
    
53. /// requrired.
    
54. #define IO_PORT_WRITE_CYCLES    2               ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
    
55. 
    
56. /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
    
57. /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
    
58. #define DAP_SWD                 1               ///< SWD Mode:  1 = available, 0 = not available
    
59. 
    
60. /// Indicate that JTAG communication mode is available at the Debug Port.
    
61. /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
    
62. #define DAP_JTAG                0               ///< JTAG Mode: 1 = available, 0 = not available.
    
63. 
    
64. /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
    
65. /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
    
66. #define DAP_JTAG_DEV_CNT        0               ///< Maximum number of JTAG devices on scan chain
    
67. 
    
68. /// Default communication mode on the Debug Access Port.
    
69. /// Used for the command \ref DAP_Connect when Port Default mode is selected.
    
70. #define DAP_DEFAULT_PORT        1               ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
    
71. 
    
72. /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
    
73. /// Used to initialize the default SWD/JTAG clock frequency.
    
74. /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
    
75. #define DAP_DEFAULT_SWJ_CLOCK   5000000         ///< Default SWD/JTAG clock frequency in Hz.
    
76. 
    
77. /// Maximum Package Size for Command and Response data.
    
78. /// This configuration settings is used to optimized the communication performance with the
    
79. /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
    
80. #define DAP_PACKET_SIZE        64              ///< USB: 64 = Full-Speed, 1024 = High-Speed.
    
81. 
    
82. /// Maximum Package Buffers for Command and Response data.
    
83. /// This configuration settings is used to optimized the communication performance with the
    
84. /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
    
85. /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
    
86. #define DAP_PACKET_COUNT       4              ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
    
87. 
    
88. /// Indicate that UART Serial Wire Output (SWO) trace is available.
    
89. /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
    
90. #define SWO_UART                0               ///< SWO UART:  1 = available, 0 = not available
    
91. 
    
92. /// Maximum SWO UART Baudrate
    
93. #define SWO_UART_MAX_BAUDRATE   10000000U       ///< SWO UART Maximum Baudrate in Hz
    
94. 
    
95. /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
    
96. /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
    
97. #define SWO_MANCHESTER          0               ///< SWO Manchester:  1 = available, 0 = not available
    
98. 
    
99. /// SWO Trace Buffer Size.
    
100. #define SWO_BUFFER_SIZE         4096U           ///< SWO Trace Buffer Size in bytes (must be 2^n)
     
101. 
     
102. 
     
103. /// Debug Unit is connected to fixed Target Device.
     
104. /// The Debug Unit may be part of an evaluation board and always connected to a fixed
     
105. /// known device.  In this case a Device Vendor and Device Name string is stored which
     
106. /// may be used by the debugger or IDE to configure device parameters.
     
107. #define TARGET_DEVICE_FIXED     0               ///< Target Device: 1 = known, 0 = unknown;
     
108. 
     
109. #if TARGET_DEVICE_FIXED
     
110. #define TARGET_DEVICE_VENDOR    ""              ///< String indicating the Silicon Vendor
     
111. #define TARGET_DEVICE_NAME      ""              ///< String indicating the Target Device
     
112. #endif
     
113. 
     
114. ///@}
     
115. 
     
116. 
     
117. static __inline void pin_out_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit)
     
118. {
     
119.     if(pin_bit >= 8)
     
120.     {
     
121.         GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
     
122.         GPIOx->CRH |= ( ((uint32_t)(0x00|0x03) & 0x0F) << ((pin_bit-8) << 2) );
     
123.     }
     
124.     else
     
125.     {
     
126.         GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
     
127.         GPIOx->CRL |= ( ((uint32_t)(0x00|0x03) & 0x0F) << ((pin_bit) << 2) );
     
128.     }
     
129. }
     
130. 
     
131. static __inline void pin_out_od_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit)
     
132. {
     
133.     if(pin_bit >= 8)
     
134.     {
     
135.         GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
     
136.         GPIOx->CRH |= ( ((uint32_t)(0x04|0x03) & 0x0F) << ((pin_bit-8) << 2) );
     
137.     }
     
138.     else
     
139.     {
     
140.         GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
     
141.         GPIOx->CRL |= ( ((uint32_t)(0x04|0x03) & 0x0F) << ((pin_bit) << 2) );
     
142.     }
     
143. }
     
144. 
     
145. static __inline void pin_in_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit, uint8_t mode)
     
146. {
     
147.     uint8_t config;
     
148.     if(mode == 1)
     
149.         config = 0x08; //Up
     
150.     else if(mode == 2)
     
151.         config = 0x08; //down
     
152.     else
     
153.         config = 0x00; //GPIO_Mode_AIN
     
154. 
     
155.     if(pin_bit >= 8)
     
156.     {
     
157.         GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
     
158.         GPIOx->CRH |= ( ((uint32_t)(config) & 0x0F) << ((pin_bit-8) << 2) );
     
159.         if(mode == 1)
     
160.             GPIOx->BSRR = (((uint32_t)0x01) << pin_bit);
     
161.         else if(mode == 2)
     
162.             GPIOx->BRR = (((uint32_t)0x01) << pin_bit);
     
163.     }
     
164.     else
     
165.     {
     
166.         GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
     
167.         GPIOx->CRL |= ( ((uint32_t)(config) & 0x0F) << ((pin_bit) << 2) );
     
168.         if(mode == 1)
     
169.             GPIOx->BSRR = (((uint32_t)0x01) << pin_bit);
     
170.         else if(mode == 2)
     
171.             GPIOx->BRR = (((uint32_t)0x01) << pin_bit);
     
172.     }
     
173. }
     
174. //**************************************************************************************************
     
175. /**
     
176. \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
     
177. \ingroup DAP_ConfigIO_gr
     
178. @{
     
179. 
     
180. Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
     
181. and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
     
182. interface of a device. The following I/O Pins are provided:
     
183. 
     
184. JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
     
185. ---------------------------- | -------------------- | ---------------------------------------------
     
186. TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
     
187. TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
     
188. TDI: Test Data Input         |                      | Output Push/Pull
     
189. TDO: Test Data Output        |                      | Input
     
190. nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
     
191. nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
     
192. 
     
193. 
     
194. DAP Hardware I/O Pin Access Functions
     
195. -------------------------------------
     
196. The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
     
197. these I/O Pins.
     
198. 
     
199. For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
     
200. This functions are provided to achieve faster I/O that is possible with some advanced GPIO
     
201. peripherals that can independently write/read a single I/O pin without affecting any other pins
     
202. of the same I/O port. The following SWDIO I/O Pin functions are provided:
     
203. - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
     
204. - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
     
205. - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
     
206. - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
     
207. */
     
208. 
     
209. 
     
210. // Configure DAP I/O pins ------------------------------
     
211. 
     
212. /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
     
213. Configures the DAP Hardware I/O pins for JTAG mode:
     
214. - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
     
215. - TDO to input mode.
     
216. */
     
217. static __inline void PORT_JTAG_SETUP(void)
     
218. {
     
219. #if (DAP_JTAG != 0)
     
220. 
     
221. #endif
     
222. }
     
223. 
     
224. /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
     
225. Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
     
226. - SWCLK, SWDIO, nRESET to output mode and set to default high level.
     
227. - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
     
228. */
     
229. static __inline void PORT_SWD_SETUP(void)
     
230. {
     
231.     // Set SWCLK HIGH
     
232.     pin_out_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit);
     
233.     SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
     
234.     // Set SWDIO HIGH
     
235.     pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
     
236.     SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
     
237. 
     
238.     pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 1);
     
239.     // Set RESET HIGH
     
240.     pin_out_od_init(nRESET_PIN_PORT, nRESET_PIN_Bit);//TODO - fix reset logic
     
241.     nRESET_PIN_PORT->BSRR = nRESET_PIN;
     
242. }
     
243. 
     
244. /** Disable JTAG/SWD I/O Pins.
     
245. Disables the DAP Hardware I/O pins which configures:
     
246. - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
     
247. */
     
248. static __inline void PORT_OFF(void)
     
249. {
     
250.     pin_in_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit, 0);
     
251.     pin_in_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit, 0);
     
252.     pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 0);
     
253. }
     
254. 
     
255. // SWCLK/TCK I/O pin -------------------------------------
     
256. 
     
257. /** SWCLK/TCK I/O pin: Get Input.
     
258. \return Current status of the SWCLK/TCK DAP hardware I/O pin.
     
259. */
     
260. static __forceinline uint32_t PIN_SWCLK_TCK_IN(void)
     
261. {
     
262.     return ((SWCLK_TCK_PIN_PORT->ODR & SWCLK_TCK_PIN) ? 1 : 0);
     
263. }
     
264. 
     
265. /** SWCLK/TCK I/O pin: Set Output to High.
     
266. Set the SWCLK/TCK DAP hardware I/O pin to high level.
     
267. */
     
268. static __forceinline void PIN_SWCLK_TCK_SET(void)
     
269. {
     
270.     SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
     
271. }
     
272. 
     
273. /** SWCLK/TCK I/O pin: Set Output to Low.
     
274. Set the SWCLK/TCK DAP hardware I/O pin to low level.
     
275. */
     
276. static __forceinline void PIN_SWCLK_TCK_CLR(void)
     
277. {
     
278.     SWCLK_TCK_PIN_PORT->BRR = SWCLK_TCK_PIN;
     
279. }
     
280. 
     
281. // SWDIO/TMS Pin I/O --------------------------------------
     
282. 
     
283. /** SWDIO/TMS I/O pin: Get Input.
     
284. \return Current status of the SWDIO/TMS DAP hardware I/O pin.
     
285. */
     
286. static __forceinline uint32_t PIN_SWDIO_TMS_IN(void)
     
287. {
     
288.     return ((SWDIO_IN_PIN_PORT->IDR & SWDIO_IN_PIN) ? 1 : 0);
     
289. }
     
290. 
     
291. /** SWDIO/TMS I/O pin: Set Output to High.
     
292. Set the SWDIO/TMS DAP hardware I/O pin to high level.
     
293. */
     
294. static __forceinline void PIN_SWDIO_TMS_SET(void)
     
295. {
     
296.     SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
     
297. }
     
298. 
     
299. /** SWDIO/TMS I/O pin: Set Output to Low.
     
300. Set the SWDIO/TMS DAP hardware I/O pin to low level.
     
301. */
     
302. static __forceinline void PIN_SWDIO_TMS_CLR(void)
     
303. {
     
304.     SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
     
305. }
     
306. 
     
307. /** SWDIO I/O pin: Get Input (used in SWD mode only).
     
308. \return Current status of the SWDIO DAP hardware I/O pin.
     
309. */
     
310. static __forceinline uint32_t PIN_SWDIO_IN(void)
     
311. {
     
312.     return ((SWDIO_IN_PIN_PORT->IDR & SWDIO_IN_PIN) ? 1 : 0);
     
313. }
     
314. 
     
315. /** SWDIO I/O pin: Set Output (used in SWD mode only).
     
316. \param bit Output value for the SWDIO DAP hardware I/O pin.
     
317. */
     
318. static __forceinline void PIN_SWDIO_OUT(uint32_t bit)
     
319. {
     
320.     if (bit & 1)
     
321.         SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
     
322.     else
     
323.         SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
     
324. }
     
325. 
     
326. /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
     
327. Configure the SWDIO DAP hardware I/O pin to output mode. This function is
     
328. called prior \ref PIN_SWDIO_OUT function calls.
     
329. */
     
330. static __forceinline void PIN_SWDIO_OUT_ENABLE(void)
     
331. {
     
332.     pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
     
333.     SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
     
334. }
     
335. 
     
336. /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
     
337. Configure the SWDIO DAP hardware I/O pin to input mode. This function is
     
338. called prior \ref PIN_SWDIO_IN function calls.
     
339. */
     
340. static __forceinline void PIN_SWDIO_OUT_DISABLE(void)
     
341. {
     
342.     pin_in_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit, 0);
     
343.     SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
     
344. }
     
345. 
     
346. 
     
347. // TDI Pin I/O ---------------------------------------------
     
348. 
     
349. /** TDI I/O pin: Get Input.
     
350. \return Current status of the TDI DAP hardware I/O pin.
     
351. */
     
352. static __forceinline uint32_t PIN_TDI_IN(void)
     
353. {
     
354.     return (0);   // Not available
     
355. }
     
356. 
     
357. /** TDI I/O pin: Set Output.
     
358. \param bit Output value for the TDI DAP hardware I/O pin.
     
359. */
     
360. static __forceinline void PIN_TDI_OUT(uint32_t bit)
     
361. {
     
362.     ;             // Not available
     
363. }
     
364. 
     
365. 
     
366. // TDO Pin I/O ---------------------------------------------
     
367. 
     
368. /** TDO I/O pin: Get Input.
     
369. \return Current status of the TDO DAP hardware I/O pin.
     
370. */
     
371. static __forceinline uint32_t PIN_TDO_IN(void)
     
372. {
     
373.     return (0);   // Not available
     
374. }
     
375. 
     
376. 
     
377. // nTRST Pin I/O -------------------------------------------
     
378. 
     
379. /** nTRST I/O pin: Get Input.
     
380. \return Current status of the nTRST DAP hardware I/O pin.
     
381. */
     
382. static __forceinline uint32_t PIN_nTRST_IN(void)
     
383. {
     
384.     return (0);   // Not available
     
385. }
     
386. 
     
387. /** nTRST I/O pin: Set Output.
     
388. \param bit JTAG TRST Test Reset pin status:
     
389.            - 0: issue a JTAG TRST Test Reset.
     
390.            - 1: release JTAG TRST Test Reset.
     
391. */
     
392. static __forceinline void PIN_nTRST_OUT(uint32_t bit)
     
393. {
     
394.     ;             // Not available
     
395. }
     
396. 
     
397. // nRESET Pin I/O------------------------------------------
     
398. 
     
399. /** nRESET I/O pin: Get Input.
     
400. \return Current status of the nRESET DAP hardware I/O pin.
     
401. */
     
402. static __forceinline uint32_t PIN_nRESET_IN(void)
     
403. {
     
404.     return ((nRESET_PIN_PORT->IDR >> nRESET_PIN_Bit) & 1);
     
405. }
     
406. 
     
407. /** nRESET I/O pin: Set Output.
     
408. \param bit target device hardware reset pin status:
     
409.            - 0: issue a device hardware reset.
     
410.            - 1: release device hardware reset.
     
411. */
     
412. // TODO - sw specific implementation should be created
     
413. 
     
414. static __forceinline void     PIN_nRESET_OUT(uint32_t bit)
     
415. {
     
416.     if (bit & 1)
     
417.         nRESET_PIN_PORT->BSRR = nRESET_PIN;
     
418.     else
     
419.         nRESET_PIN_PORT->BRR = nRESET_PIN;
     
420. }
     
421. 
     
422. //**************************************************************************************************
     
423. /**
     
424. \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
     
425. \ingroup DAP_ConfigIO_gr
     
426. @{
     
427. 
     
428. CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
     
429. 
     
430. It is recommended to provide the following LEDs for status indication:
     
431. - Connect LED: is active when the DAP hardware is connected to a debugger.
     
432. - Running LED: is active when the debugger has put the target device into running state.
     
433. */
     
434. 
     
435. /** Debug Unit: Set status of Connected LED.
     
436. \param bit status of the Connect LED.
     
437.            - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
     
438.            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
     
439. */
     
440. static __inline void LED_CONNECTED_OUT(uint32_t bit)
     
441. {
     
442.     if (bit & 1)
     
443.         CONNECTED_LED_PORT->BRR = CONNECTED_LED_PIN; // LED on
     
444.     else
     
445.         CONNECTED_LED_PORT->BSRR = CONNECTED_LED_PIN;// LED off
     
446. }
     
447. 
     
448. /** Debug Unit: Set status Target Running LED.
     
449. \param bit status of the Target Running LED.
     
450.            - 1: Target Running LED ON: program execution in target started.
     
451.            - 0: Target Running LED OFF: program execution in target stopped.
     
452. */
     
453. static __inline void LED_RUNNING_OUT(uint32_t bit)
     
454. {
     
455.     ;             // Not available
     
456. }
     
457. 
     
458. ///@}
     
459. 
     
460. 
     
461. //**************************************************************************************************
     
462. /**
     
463. \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
     
464. \ingroup DAP_ConfigIO_gr
     
465. @{
     
466. 
     
467. CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
     
468. */
     
469. 
     
470. /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
     
471. This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
     
472. Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
     
473. - I/O clock system enabled.
     
474. - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
     
475. - for nTRST, nRESET a weak pull-up (if available) is enabled.
     
476. - LED output pins are enabled and LEDs are turned off.
     
477. */
     
478. static __inline void DAP_SETUP(void)
     
479. {
     
480.     /* Enable port clock */
     
481.     __HAL_RCC_GPIOA_CLK_ENABLE();
     
482.     __HAL_RCC_GPIOB_CLK_ENABLE();
     
483.     __HAL_RCC_GPIOC_CLK_ENABLE();
     
484.     __HAL_RCC_GPIOD_CLK_ENABLE();
     
485.     /* Configure I/O pin SWCLK */
     
486.     pin_out_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit);
     
487.     SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
     
488. 
     
489.     pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
     
490.     SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
     
491. 
     
492.     pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 1);
     
493. 
     
494.     pin_out_od_init(nRESET_PIN_PORT, nRESET_PIN_Bit);
     
495.     nRESET_PIN_PORT->BSRR = nRESET_PIN;
     
496. 
     
497.     pin_out_init(CONNECTED_LED_PORT, CONNECTED_LED_PIN_Bit);
     
498.     CONNECTED_LED_PORT->BSRR = CONNECTED_LED_PIN;
     
499. }
     
500. 
     
501. /** Reset Target Device with custom specific I/O pin or command sequence.
     
502. This function allows the optional implementation of a device specific reset sequence.
     
503. It is called when the command \ref DAP_ResetTarget and is for example required
     
504. when a device needs a time-critical unlock sequence that enables the debug port.
     
505. \return 0 = no device specific reset sequence is implemented.\n
     
506.         1 = a device specific reset sequence is implemented.
     
507. */
     
508. static __inline uint32_t RESET_TARGET(void)
     
509. {
     
510.     return (0);              // change to '1' when a device reset sequence is implemented
     
511. }
     
512. 
     
513. ///@}
     
514. 
     
515. 
     
516. #endif /* __DAP_CONFIG_H__ */
     

复制代码