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发表于 2021-8-7 10:35:23
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详细说明如下:
/*
*********************************************************************************************************
* Cortex-M
* Critical Section Management
*
* Method #1: Disable/Enable interrupts using simple instructions. After critical section, interrupts
* will be enabled even if they were disabled before entering the critical section.
* NOT IMPLEMENTED
*
* Method #2: Disable/Enable interrupts by preserving the state of interrupts. In other words, if
* interrupts were disabled before entering the critical section, they will be disabled when
* leaving the critical section.
* NOT IMPLEMENTED
*
* Method #3: Disable/Enable interrupts by preserving the state of interrupts. Generally speaking you
* would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
* disable interrupts. 'cpu_sr' is allocated in all of uC/OS-II's functions that need to
* disable interrupts. You would restore the interrupt disable state by copying back 'cpu_sr'
* into the CPU's status register.
*********************************************************************************************************
*/
#define OS_CRITICAL_METHOD 3u
#if OS_CRITICAL_METHOD == 3u
/* Save current BASEPRI priority lvl for exception... */
/* .. and set BASEPRI to CPU_CFG_KA_IPL_BOUNDARY */
#define OS_ENTER_CRITICAL() do { cpu_sr = OS_CPU_SR_Save(CPU_CFG_KA_IPL_BOUNDARY << (8u - CPU_CFG_NVIC_PRIO_BITS));} while (0)
/* Restore CPU BASEPRI priority level. */
#define OS_EXIT_CRITICAL() do { OS_CPU_SR_Restore(cpu_sr);} while (0)
#endif
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