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发表于 2021-12-29 14:22:08
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显示全部楼层
降低到550MHz可以运行.
/**
* @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
* @note Enabling/disabling those Clocks can be done only when the PLL2 is disabled,
* This is mainly used to save Power.
* @param __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted
* This parameter can be one of the following values:
* @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
* @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
* @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
*
* (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise.
* (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise.
* (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
*
* @retval None
*/ |
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