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此程序实现简单的ALU
`define plus 3'd0
`define minus 3'd1
`define band 3'd2
`define bor 3'd3
`define unegate 3'd4
module verilog_prj(out,opcode,a,b);
output[7:0] out;
reg[7:0] out;
input[2:0] opcode;
input[7:0] a,b; //操作数。
always@(opcode or a or b) //电平敏感的 always块
begin
case(opcode)
`plus: out = a+b; //加操作。
`minus: out = a-b; //减操作。
`band: out = a&b; //求与。
`bor: out = a|b; //求或。
`unegate: out=~a; //求反。
default: out=8'hx;//未收到指令时,输出任意态。
endcase
end
endmodule
测试模块
`timescale 1 ns/ 1 ps
module verilog_prj_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg [7:0] a;
reg [7:0] b;
reg [2:0] opcode;
// wires
wire [7:0] out;
// assign statements (if any)
verilog_prj i1 (
// port map - connection between master ports and signals/registers
.a(a),
.b(b),
.opcode(opcode),
.out(out)
);
parameter times=5;
initial
begin
a={$random}%256; //Give a radom number blongs to [0,25 5] .
b={$random}%256; //Give a radom number blongs to [0,25 5].
opcode=3'h0;
repeat(times)
begin
#100 a={$random}%256; //Give a radom number.
b={$random}%256; //Give a radom number.
opcode=opcode+1;
end
#100 $stop;
end
endmodule |
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