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此程序搞的有点麻烦,先不做分析了。
module p_to_s(D_in,T0,data,SEND,ESC,ADD_100);
output D_in,T0; // D_in 是串行输出,T0是移位时钟并给
// CPU中断,以确定何时给出下个数据。
input [7:0] data; //并行输入的数据。
input SEND,ESC,ADD_100; //SEND、ESC 共同决定是否进行并到串
//的数据转化。ADD_100 决定何时置数。
wire D_in,T0;
reg [7:0] DATA_Q,DATA_Q_buf;
assign T0 = ! (SEND & ESC); //形成移位时钟。.
assign D_in = DATA_Q[7]; //给出串行数据。
always @(posedge T0 or negedge ADD_100) //ADD_100下沿置数,T0 上沿移位。
begin
if(!ADD_100)
DATA_Q = data;
else
begin
DATA_Q_buf = DATA_Q<<1; //DATA_Q_buf 作为中介,以令综合器
DATA_Q = DATA_Q_buf; //能辨明。
end
end
endmodule
module s_to_p(T1, data, D_out,DSC,TAKE,ADD_101);
output T1; //给CPU 中断,以确定CPU 何时取转化
//得到的并行数据。
output [7:0] data;
input D_out, DSC, TAKE, ADD_101; //D_out提供输入串行数据。DSC、TAKE
// 共同决定何时取数。
wire [7:0] data;
wire T1,clk2;
reg [7:0] data_latch, data_latch_buf;
assign clk2 = DSC & TAKE ; //提供移位时钟。
assign T1 = !clk2;
assign data = (!ADD_101) ? data_latch : 8'bz;
always@(posedge clk2)
begin
data_latch_buf = data_latch << 1; //data_latch _buf作缓冲
data_latch = data_latch_buf; //,以令综合器能辩明。
data_latch[0] = D_out;
end
endmodule
顶层代码
`include "./p_to_s.v"
`include "./s_to_p.v"
module sys(D_in,T0,T1, data, D_out,SEND,ESC,DSC,TAKE,ADD_100,AD D_101);
input D_out,SEND,ESC,DSC,TAKE,ADD_100,ADD_101;
inout [7:0] data;
output D_in,T0,T1;
p_to_s p_to_s(.D_in(D_in),.T0(T0),.data(data),
.SEND(SEND),.ESC(ESC),.ADD_100(ADD_100));
s_to_p s_to_p(.T1(T1),.data(data),.D_out(D_out),
.DSC(DSC),.TAKE(TAKE),.ADD_101(ADD_101));
endmodule
测试代码
`timescale 1ns/100ps
`include "./sys.v"
module Top;
reg D_out,SEND,ESC,DSC,TAKE,ADD_100,ADD_101;
reg[7:0] data_buf;
wire [7:0] data;
wire clk2;
assign data = (ADD_101) ? data_buf : 8'bz;
//data 在sys 中是inout 型变量,ADD_101
//控制 data是作为输入还是进行输出。
assign clk2 =DSC && TAKE;
initial
begin
SEND = 0;
ESC = 0;
DSC = 1;
TAKE = 1;
ADD_100 = 1;
ADD_101 = 1;
end
initial
begin
data_buf = 8'b10000001;
#90 ADD_100 = 0;
#100 ADD_100 = 1;
end
always
begin
#50;
SEND = ~SEND;
ESC = ~ESC;
end
initial
begin
#1500 ;
SEND = 0;
ESC = 0;
DSC = 1;
TAKE = 1;
ADD_100 = 1;
ADD_101 = 1;
D_out = 0;
#1150 ADD_101 = 0;
#100 ADD_101 =1;
#100 $stop;
end
always
begin
#50 ;
DSC = ~DSC;
TAKE = ~TAKE;
end
always @(negedge clk2) D_out = ~D_out;
sys sys(.D_in(D_in),.T0(T0),.T1(T1),.data(data),.D_out(D_out ),
.ADD_101(ADD_101), .SEND(SEND),.ESC(ESC),.DSC(DSC ),
.TAKE(TAKE),.ADD_100(ADD_100 ));
endmodule |
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