面对RT1052复杂的时钟配置，使用软件MCUXpresso Config Tools方可一目了然

eric2013

    官方评估板的时钟配置代码是通过这个软件生成的，即clock_config.c文件。首次使用这个软件务必要将clock_config.c文件中的函数在配置软件MCUXpresso Config Tools一个一个捋顺一遍，这样心理就踏实多了，要不老是感觉那里没有整明白。官网下载地址：链接

1、根据自己的电脑系统版本选择即可，操作几次基本就熟练了。


2、软件效果：

3、比如配置了个SDRAM的时钟，一目了然：

eric2013

举例clock_config.c中的配置：

1. /*
   
2. * The Clear BSD License
   
3. * Copyright 2017 NXP
   
4. * All rights reserved.
   
5. *
   
6. * Redistribution and use in source and binary forms, with or without modification,
   
7. * are permitted (subject to the limitations in the disclaimer below) provided
   
8. *  that the following conditions are met:
   
9. *
   
10. * o Redistributions of source code must retain the above copyright notice, this list
    
11. *   of conditions and the following disclaimer.
    
12. *
    
13. * o Redistributions in binary form must reproduce the above copyright notice, this
    
14. *   list of conditions and the following disclaimer in the documentation and/or
    
15. *   other materials provided with the distribution.
    
16. *
    
17. * o Neither the name of the copyright holder nor the names of its
    
18. *   contributors may be used to endorse or promote products derived from this
    
19. *   software without specific prior written permission.
    
20. *
    
21. * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
    
22. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
    
23. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
    
24. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
    
25. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
    
26. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
    
27. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
    
28. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
    
29. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    
30. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
    
31. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    
32. */
    
33. /*
    
34. * How to setup clock using clock driver functions:
    
35. *
    
36. * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
    
37. *
    
38. * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
    
39. *
    
40. * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
    
41. *
    
42. * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
    
43. *
    
44. * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
    
45. *
    
46. */
    
47. 
    
48. /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
    
49. !!GlobalInfo
    
50. product: Clocks v4.0
    
51. processor: MIMXRT1052xxxxx
    
52. package_id: MIMXRT1052DVL6B
    
53. mcu_data: i_mx_1_0
    
54. processor_version: 0.0.0
    
55. board: IMXRT1050-EVKB
    
56. * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
    
57. 
    
58. #include "clock_config.h"
    
59. 
    
60. /*******************************************************************************
    
61. * Definitions
    
62. ******************************************************************************/
    
63. 
    
64. /*******************************************************************************
    
65. * Variables
    
66. ******************************************************************************/
    
67. /* System clock frequency. */
    
68. extern uint32_t SystemCoreClock;
    
69. 
    
70. /*******************************************************************************
    
71. ************************ BOARD_InitBootClocks function ************************
    
72. ******************************************************************************/
    
73. void BOARD_InitBootClocks(void)
    
74. {
    
75.     BOARD_BootClockRUN();
    
76. }
    
77. 
    
78. /*******************************************************************************
    
79. ********************** Configuration BOARD_BootClockRUN ***********************
    
80. ******************************************************************************/
    
81. /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
    
82. !!Configuration
    
83. name: BOARD_BootClockRUN
    
84. called_from_default_init: true
    
85. outputs:
    
86. - {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
    
87. - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
    
88. - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
    
89. - {id: CLK_1M.outFreq, value: 1 MHz}
    
90. - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
    
91. - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
    
92. - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
    
93. - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
    
94. - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
    
95. - {id: FLEXSPI_CLK_ROOT.outFreq, value: 37.5 MHz}
    
96. - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
    
97. - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
    
98. - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
    
99. - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
    
100. - {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
     
101. - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
     
102. - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
     
103. - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
     
104. - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
     
105. - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
     
106. - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
     
107. - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
     
108. - {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
     
109. - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
     
110. - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
     
111. - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
     
112. settings:
     
113. - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
     
114. - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
     
115. - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
     
116. - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
     
117. - {id: CCM.SEMC_PODF.scale, value: '8'}
     
118. - {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
     
119. - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
     
120. - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
     
121. - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
     
122. - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
     
123. - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
     
124. - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
     
125. - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
     
126. - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
     
127. - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
     
128. - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
     
129. - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
     
130. - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
     
131. - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
     
132. - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
     
133. - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
     
134. - {id: CCM_ANALOG.PLL4.denom, value: '50'}
     
135. - {id: CCM_ANALOG.PLL4.div, value: '47'}
     
136. - {id: CCM_ANALOG.PLL5.denom, value: '1'}
     
137. - {id: CCM_ANALOG.PLL5.div, value: '40'}
     
138. - {id: CCM_ANALOG.PLL5.num, value: '0'}
     
139. - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
     
140. sources:
     
141. - {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
     
142. - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
     
143. * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
     
144. 
     
145. /*******************************************************************************
     
146. * Variables for BOARD_BootClockRUN configuration
     
147. ******************************************************************************/
     
148. const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
     
149.     .loopDivider = 88, /* PLL loop divider, Fout = Fin * 50 */
     
150. };
     
151. const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
     
152.     .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
     
153.     .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
     
154.     .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
     
155. };
     
156. const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
     
157.     .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
     
158. };
     
159. /*******************************************************************************
     
160. * Code for BOARD_BootClockRUN configuration
     
161. ******************************************************************************/
     
162. void BOARD_BootClockRUN(void)
     
163. {
     
164.     /* Init RTC OSC clock frequency. */
     
165.     CLOCK_SetRtcXtalFreq(32768U);
     
166.     /* Set XTAL 24MHz clock frequency. */
     
167.     CLOCK_SetXtalFreq(24000000U);
     
168.     /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
     
169.     CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
     
170.     CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
     
171.     /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz. */
     
172.     DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
     
173.     /* Waiting for DCDC_STS_DC_OK bit is asserted */
     
174.     while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
     
175.     {
     
176.     }
     
177.     /* Init ARM PLL. */
     
178.     CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
     
179.     /* Init System PLL. */
     
180. #ifndef SKIP_SYSCLK_INIT
     
181.     CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
     
182. #endif
     
183.     /* Init Usb1 PLL. */
     
184. #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
     
185.     CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
     
186. #endif
     
187.     /* Enbale Audio PLL output. */
     
188.     CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
     
189.     /* Enbale Video PLL output. */
     
190.     CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
     
191.     /* Enable ENET PLL output. */
     
192.     CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
     
193.     CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
     
194.     /* Set periph clock2 clock source. */
     
195.     CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
     
196.     /* Set PERIPH_CLK2_PODF. */
     
197.     CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
     
198.     /* Set periph clock source. */
     
199.     CLOCK_SetMux(kCLOCK_PeriphMux, 0);
     
200.     /* Set AHB_PODF. */
     
201.     CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
     
202.     /* Set IPG_PODF. */
     
203.     CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
     
204.     /* Set ARM_PODF. */
     
205.     CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
     
206.     /* Set preperiph clock source. */
     
207.     CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
     
208.     /* Set PERCLK_PODF. */
     
209.     CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
     
210.     /* Set per clock source. */
     
211.     CLOCK_SetMux(kCLOCK_PerclkMux, 0);
     
212.     /* Set Usdhc1 clock source. */
     
213.     CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
     
214.     /* Set USDHC1_PODF. */
     
215.     CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
     
216.     /* Set Usdhc2 clock source. */
     
217.     CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
     
218.     /* Set USDHC2_PODF. */
     
219.     CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
     
220. #ifndef SKIP_SYSCLK_INIT
     
221.     /* Set Semc alt clock source. */
     
222.     CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
     
223.     /* Set Semc clock source. */
     
224.     CLOCK_SetMux(kCLOCK_SemcMux, 0);
     
225.     /* Set SEMC_PODF. */
     
226.     CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
     
227. #endif
     
228. #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
     
229.     /* Set Flexspi clock source. */
     
230.     CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
     
231.     /* Set FLEXSPI_PODF. */
     
232.     CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
     
233. #endif
     
234.     /* Set Csi clock source. */
     
235.     CLOCK_SetMux(kCLOCK_CsiMux, 0);
     
236.     /* Set CSI_PODF. */
     
237.     CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
     
238.     /* Set Lpspi clock source. */
     
239.     CLOCK_SetMux(kCLOCK_LpspiMux, 2);
     
240.     /* Set LPSPI_PODF. */
     
241.     CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
     
242.     /* Set Trace clock source. */
     
243.     CLOCK_SetMux(kCLOCK_TraceMux, 2);
     
244.     /* Set TRACE_PODF. */
     
245.     CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
     
246.     /* Set Sai1 clock source. */
     
247.     CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
     
248.     /* Set SAI1_CLK_PRED. */
     
249.     CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
     
250.     /* Set SAI1_CLK_PODF. */
     
251.     CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
     
252.     /* Set Sai2 clock source. */
     
253.     CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
     
254.     /* Set SAI2_CLK_PRED. */
     
255.     CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
     
256.     /* Set SAI2_CLK_PODF. */
     
257.     CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
     
258.     /* Set Sai3 clock source. */
     
259.     CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
     
260.     /* Set SAI3_CLK_PRED. */
     
261.     CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
     
262.     /* Set SAI3_CLK_PODF. */
     
263.     CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
     
264.     /* Set Lpi2c clock source. */
     
265.     CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
     
266.     /* Set LPI2C_CLK_PODF. */
     
267.     CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
     
268.     /* Set Can clock source. */
     
269.     CLOCK_SetMux(kCLOCK_CanMux, 2);
     
270.     /* Set CAN_CLK_PODF. */
     
271.     CLOCK_SetDiv(kCLOCK_CanDiv, 1);
     
272.     /* Set Uart clock source. */
     
273.     CLOCK_SetMux(kCLOCK_UartMux, 0);
     
274.     /* Set UART_CLK_PODF. */
     
275.     CLOCK_SetDiv(kCLOCK_UartDiv, 0);
     
276.     /* Set Lcdif pre clock source. */
     
277.     CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
     
278.     /* Set LCDIF_PRED. */
     
279.     CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
     
280.     /* Set LCDIF_CLK_PODF. */
     
281.     CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
     
282.     /* Set Spdif clock source. */
     
283.     CLOCK_SetMux(kCLOCK_SpdifMux, 3);
     
284.     /* Set SPDIF0_CLK_PRED. */
     
285.     CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
     
286.     /* Set SPDIF0_CLK_PODF. */
     
287.     CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
     
288.     /* Set Flexio1 clock source. */
     
289.     CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
     
290.     /* Set FLEXIO1_CLK_PRED. */
     
291.     CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
     
292.     /* Set FLEXIO1_CLK_PODF. */
     
293.     CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
     
294.     /* Set Flexio2 clock source. */
     
295.     CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
     
296.     /* Set FLEXIO2_CLK_PRED. */
     
297.     CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
     
298.     /* Set FLEXIO2_CLK_PODF. */
     
299.     CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
     
300.     /* Set Pll3 sw clock source. */
     
301.     CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
     
302.     /* Set lvds1 clock source. */
     
303.     CCM_ANALOG->MISC1 =
     
304.         (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
     
305.     /* Set SystemCoreClock variable. */
     
306.     SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
     
307. }
     

复制代码

XINGGY

能不能详细介绍一下怎么打开这个时钟配置界面的，我用该软件时报不支持该处理器

eric2013

XINGGY 发表于 2018-5-18 16:13
能不能详细介绍一下怎么打开这个时钟配置界面的，我用该软件时报不支持该处理器

好的，今天晚些时候我发个帖子。

eric2013

XINGGY 发表于 2018-5-18 16:13
能不能详细介绍一下怎么打开这个时钟配置界面的，我用该软件时报不支持该处理器

发了个帖子：
http://www.armbbs.cn/forum.php?mod=viewthread&tid=86732