不是单块
[C] 纯文本查看 复制代码 #define CD_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
#define CD_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB (2x64KB) system data RAM accessible over DTCM */
#define CD_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
#define CD_AXISRAM1_BASE (0x24000000UL) /*!< Base address of : (up to 256KB) system data RAM1 accessible over over AXI */
#define CD_AXISRAM2_BASE (0x24040000UL) /*!< Base address of : (up to 384KB) system data RAM2 accessible over over AXI */
#define CD_AXISRAM3_BASE (0x240A0000UL) /*!< Base address of : (up to 384KB) system data RAM3 accessible over over AXI */
#define CD_AHBSRAM1_BASE (0x30000000UL) /*!< Base address of : (up to 64KB) system data RAM1 accessible over over AXI->AHB Bridge */
#define CD_AHBSRAM2_BASE (0x30010000UL) /*!< Base address of : (up to 64KB) system data RAM2 accessible over over AXI->AHB Bridge */
#define SRD_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
#define SRD_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(32 KB) over AXI->AHB Bridge
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