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发表于 2018-10-29 00:02:30
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B4.3 SWD interface
The SWD protocol uses a synchronous serial interface, which comprises a single bidirectional data signal, and a clock signal.
This section gives an overview of the physical SWD interface.
B4.3.1 Line interface
The SWD interface uses a single bidirectional data pin, SWDIO. The same signal is used for both host and target sourced signals.
The SWD interface is synchronous, and requires a clock pin, SWCLK.
When the target samples SWDIO, sampling is performed on the rising edge of SWCLK. When the target drives SWDIO, or stops driving it, signal changes are performed on the rising edge of SWCLK.
The clock can be sourced from the target and exported, or provided by the host. This clock is then used by the host as a reference for generation and sampling of data so that the target is not required to perform any over-sampling.
Both the target and host can drive the bus HIGH and LOW or tristate it. The ports must be able to tolerate short periods of contention that might occur because of a loss of synchronization.
The clock can be asynchronous to any system clock, including the debug logic clock. The SWD interface clock can be stopped when the debug port is idle, see About the SWD protocol on page B4-110.
简单翻译：SWD接口使用单个双向数据引脚SWDIO。主机和目标都使用相同的信号。
SWD接口是同步的，需要一个时钟引脚，SWCLK。
当目标采样SWDIO时，采样在SWCK的上升沿上进行。当目标驱动SWDIO或停止驱动时，在SWCK的上升沿上执行信号变化。
时钟可以由目标提供也可以由主机提供。然后，主机将该时钟用作生成和采样数据的参考，从而不需要目标执行任何过采样。
目标和主机都可以驱动总线高或低或三态。端口必须能够容忍由于丢失同步而可能发生的短周期争用。
时钟可以与任何系统时钟异步，包括调试逻辑时钟。当调试端口空闲时，SWD接口时钟可以停止，请参阅B4-110页上的SWD协议。
B4.3.2 Line pull-up
To make sure that the line is in a known state when neither host nor target is driving the line, a 100KΩ pull-up is
required at the target. This pull-up can only be relied on to maintain the state of the wire. If the wire is driven LOW
and released, the pull-up resistor eventually returns the line to the HIGH state, but this process takes many clock
cycles.
The pull-up is intended to prevent false detection of signals when no host is connected, and must be of a suitably
high value to reduce current consumption from the target when the host actively pulls down the line
为了确保当主机和目标都没有驱动口线时，该口线处于已知状态，100kΩ上拉电阻是需要的。这种上拉只用于保持口线的状态。如果口线被驱动低然后释放，上拉电阻最终将口线返回到高状态，但是这个过程需要很多时钟周期。
上拉是为了防止在没有主机连接时信号的错误检测，并且必须是适当的。当主机主动下线时，高值可以减少来自目标的电流消耗。
注释：每当口线被驱动低时，一个小电流从目标排出。如果接口是连接状态 当目标必须使用低功耗模式时，主机必须保持高电平或复位。直到接口被激活。
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发表于 2018-10-28 23:44:49
