识别Cortex-M 内核的方法（M0 - M7）

armfly

查阅本资料的目的仅仅用于实现脱机烧录功能时，打印内核信息
原文地址 https://developer.arm.com/ip-products/processors/cortex-m

Cortex-M comparison table

Feature	Cortex-M0	Cortex-M0+	Cortex-M1	Cortex-M23	Cortex-M3	Cortex-M4	Cortex-M33	Cortex-M35P	Cortex-M55	Cortex-M7
Instruction Set Architecture	Armv6-M	Armv6-M	Armv6-M	Armv8-M Baseline	Armv7-M	Armv7-M	Armv8-M Mainline	Armv8-M Mainline	Armv8.1-M Mainline Helium	Armv7-M
	Thumb, Thumb-2	Thumb, Thumb-2	Thumb, Thumb-2	Thumb, Thumb-2	Thumb, Thumb-2	Thumb, Thumb-2	Thumb, Thumb-2	Thumb, Thumb-2	Thumb, Thumb-2	Thumb, Thumb-2
DMIPS/MHz range*	0.87-1.27	0.95-1.36	0.8	0.98	1.25-1.89	1.25-1.95	1.5	1.5	1.6	2.14-3.23
CoreMark®/MHz*	2.33	2.46	1.85	2.64	3.34	3.42	4.02	4.02	4.2	5.01
Pipeline Stages	3	2	3	2	3	3	3	3	4	6
Memory Protection Unit (MPU)	No	Yes (option)	No	Yes (option) (2 x)	Yes (option)	Yes (option)	Yes (option) (2 x)	Yes (option) (2 x)	Yes (option) (2 x)	Yes (option)
Maximum MPU Regions	0	8	0	16	8	8	16	16	16	16
Trace (ETM or MTB)	No	MTB (option)	No	MTB (option) or ETMv3 (option)	ETMv3 (option)	ETMv3 (option)	MTB (option) and/or ETMv4 (option)	MTB (option) and/or ETMv4 (option)	ETMv4 (option)	ETMv4 (option)
Digital Signal Processing (DSP) extension	No	No	No	No	No	Yes	Yes (option)	Yes (option)	Yes (option)	Yes
Floating Point Hardware	No	No	No	No	No	Yes (scalar SP)	Yes (scalar SP)	Yes (scalar SP)	Yes (scalar HP + SP + DP) (vector HP + SP)	Yes (scalar SP + DP)
Systick Timer	Yes (option)	Yes (option)	Yes (option)	Yes (2 x)	Yes	Yes	Yes (2 x)	Yes (2 x)	Yes (2 x)	Yes
Built-in Caches	No	No	No	No	No	No	No	Yes (option 2- 16kB	Yes (option)	Yes (option 4-64kB
								I-cache	I-cache and D-cache	I-cache, D-cache)
Tightly Coupled Memory	No	No	Yes	No	No	No	No	No	Yes (option 0-16MB I-TCM/D-TCM)	Yes (option 0-16MB I-TCM/D-TCM)
TrustZone for Armv8-M	No	No	No	Yes (option)	No	No	Yes (option)	Yes (option)	Yes (option)	No
Coprocessor Interface	No	No	No	No	No	No	Yes (option)	Yes (option)	Yes (option)	No
Bus Protocol	AHB Lite	AHB Lite, Fast I/O	AHB Lite	AHB5, Fast I/O	AHB Lite, APB	AHB Lite, APB	AHB5, APB	AHB5, APB	AXI5 (main bus), AHB (peripheral bus, TCM slave port and debug)	AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support	Yes	Yes	No	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Integrated Interrupt Controller (NVIC)	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Maximum # External Interrupts	32	32	32	240	240	240	480	480	480	240
Hardware Divide	No	No	No	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Single Cycle Multiply	Yes (option)	Yes (option)	No	Yes	Yes	Yes	Yes	Yes	Yes	Yes
CMSIS Support	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Dual Core Lock-Step Support	No	No	No	Yes	No	No	Yes	Yes	No	Yes
Arm Custom Instructions	No	No	No	No	No	No	Yes	No	Yes (available in 2021)	No
Common Criteria certification	No	No	No	No	No	No	Yes	Yes	No	No

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

HP = Half Precision

armfly

读CPUID (0xE000ED00)，根据其中的字段Partno识别。
以下数据根据每个系列的手册汇总。
缺M35P
【M0】
[31:24] Implementer  Implementer code: 0x41 = ARM.
[23:20] Variant  Implementation defined. In ARM implementations this is the major revision number n in the rn part of the rnpn revision status,
    Product revision status: 0x0.
[19:16] Constant    Indicates the architecture, ARMv6-M: 0xC.
[15:4]  Partno  Indicates part number, Cortex-M0: 0xC20.
[3:0]   Revision    Indicates revision. In ARM implementations this is the minor revision number n in the pn part of the rnpn revision status,
    see Product revision status. For example, for release r0p0: 0x0.

【M0+】
[31:24] IMPLEMENTER Implementer code: 0x41 ARM.
[23:20] VARIANT Major revision number n in the rnpm revision status. See Product revision status:0x0.
[19:16] ARCHITECTURE    Indicates the architecture, ARMv6-M: 0xC.
[15:4]  PARTNO  Indicates part number, Cortex-M0+: 0xC60.
[3:0]   REVISION    Minor revision number m in the rnpm revision status. See Product revision status. 0x1.

【M1】
[31:24] IMPLEMENTER  Implementer code:0x41 = ARM
[23:20] VARIANT  Implementation defined variant number: 0x0 for r0p1
[19:16] Constant    Reads as 0xC
[15:4]  PARTNO  Number of processor within family: 0xC21
[3:0]   REVISION    Implementation defined revision number: 0x1 = r0p1   

【M23】
[31:24] IMPLEMENTER Implementer code:0x41 = Arm.
[23:20] VARIANT Major revision number n in the rnpm revision status: 0x1 = Revision 1.
[19:16] ARCHITECTURE  Constant that defines the architecture of the processor: 0xC = Armv8-M architecture.
[15:4]  PARTNO  Part number of the processor: 0xD20 = Cortex-M23.
[3:0]   REVISION   Minor revision number m in the rnpm revision status: 0x0 = Patch 0.

【M3】
[31:24] IMPLEMENTER Indicates implementer: 0x41 = ARM?
[23:20] VARIANT Indicates processor revision: 0x0 = Revision 0
[19:16] (Constant)  Reads as 0xF
[15:4]  PARTNO  Indicates part number: 0xC23 = Cortex??M3
[3:0]   REVISION    Indicates patch release: 0x1= Patch 1.

【M33】
[31:24] Implementer Implementer code: 0x41  Arm?
[23:20] Variant Variant number, the n value in the rnpm product revision identifier: 0x0    Revision 0
[19:16] Constant    Reads as 0xF
[15:4]  PartNo  Part number of the processor: 0xD21 Cortex??M33
[3:0]   Revision    Revision number, the m value in the rnpm product revision identifier: 0x3   Patch 3.

【M4】
[31:24] IMPLEMENTER Indicates implementer: 0x41 = Arm?
[23:20] VARIANT Indicates processor revision: 0x0 = Revision 0
[19:16] (Constant)  Reads as 0xF
[15:4]  PARTNO  Indicates part number: 0xC24 = Cortex?-M4
[3:0]   REVISION    Indicates patch release: 0x1= Patch 1.

【M55】
[31:24] Implementer Implementer code: 0x41  Arm?Limited
[23:20] Variant Variant number, the n value in the rnpm product revision identifier: 0x0    Revision 0
[19:16] Architecture    Reads as 0b1111, Armv8.1?M with Main Extension
[15:4]  PartNo  Part number of the processor: 0xD22 Cortex?-M55
[3:0]   Revision    Revision number, the m value in the rnpm product revision identifier: 0x1   Patch 1.

【M7】
[31:24] IMPLEMENTER  Indicates implementer: 0x41  Arm.
[23:20] VARIANT  Indicates processor revision: 0x0 Revision 0. 0x1 Revision 1.
[19:16] ARCHITECTURE Reads as 0xF.
[15:4]  PARTNO  Indicates part number: 0xC27  Cortex-M7.
[3:0]   REVISION  Indicates patch release: 0x0  Patch 0.

armfly

开始以为是M3和M4的Partno是相同的，找了半天资料如何判断M3和M4内核。原来是ARM的有个文档笔误。


正确的是C23.  错误文档写的是C24
https://developer.arm.com/docs/100165/0201/system-control/cpuid-base-register-cpuid

eric2013

armfly 发表于 2020-6-29 02:33
读CPUID (0xE000ED00)，根据其中的字段Partno识别。
以下数据根据每个系列的手册汇总。
缺M35P

M35P是ARM出的防物理破解内核，莫非他们限制了。