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发表于 2024-3-15 13:18:18
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#include "dm9162.h"
lan8742_Object_t DM9162;
TX_THREAD *netx_thread_ptr;
static UINT _nx_driver_hardware_initialize(NX_IP_DRIVER *driver_req_ptr)
{
INT PHYLinkState;
UINT duplex, speed = 0;
lan8742_IOCtx_t DM9162_IOCtx = {ETH_PHY_IO_Init,
ETH_PHY_IO_DeInit,
ETH_PHY_IO_WriteReg,
ETH_PHY_IO_ReadReg,
ETH_PHY_IO_GetTick};
NX_PACKET *packet_ptr;
UINT i;
ETH_DMADescTypeDef *DMATxDesc;
ETH_DMADescTypeDef *DMARxDesc = nx_driver_information.nx_driver_information_dma_rx_descriptors;
HAL_ETH_MspInit(NULL);
/* Default to successful return. */
driver_req_ptr -> nx_ip_driver_status = NX_SUCCESS;
/* Setup indices. */
nx_driver_information.nx_driver_information_receive_current_index = 0;
nx_driver_information.nx_driver_information_transmit_current_index = 0;
nx_driver_information.nx_driver_information_transmit_release_index = 0;
/* Clear the number of buffers in use counter. */
nx_driver_information.nx_driver_information_number_of_transmit_buffers_in_use = 0;
/* Make sure there are receive packets... otherwise, return an error. */
if (nx_driver_information.nx_driver_information_packet_pool_ptr == NULL)
{
/* There must be receive packets. If not, return an error! */
return(NX_DRIVER_ERROR);
}
EthHandle.Instance = ETH;
EthHandle.Init.MACAddr = _nx_driver_hardware_address;
EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
EthHandle.Init.PhyAddress = LAN8742_PHY_ADDR;
printf("程序执行到这里了");
/* Set PHY IO functions */
LAN8742_RegisterBusIO(&DM9162, &DM9162_IOCtx);
printf("程序meiyou执行到这里了");
/* Initialize the DM9162 ETH PHY */
LAN8742_Init(&DM9162);
printf("LAN8742_Init");
PHYLinkState = LAN8742_GetLinkState(&DM9162);
printf("PHYLinkState = %d\r\n",PHYLinkState);
while(PHYLinkState <= LAN8742_STATUS_LINK_DOWN)
{
PHYLinkState = LAN8742_GetLinkState(&DM9162);
printf("PHYLinkStateX = %d\r\n",PHYLinkState);
tx_thread_sleep(100);
}
switch (PHYLinkState)
{
case LAN8742_STATUS_100MBITS_FULLDUPLEX:
duplex = ETH_MODE_FULLDUPLEX;
speed = ETH_SPEED_100M;
break;
case LAN8742_STATUS_100MBITS_HALFDUPLEX:
duplex = ETH_MODE_HALFDUPLEX;
speed = ETH_SPEED_100M;
break;
case LAN8742_STATUS_10MBITS_FULLDUPLEX:
duplex = ETH_MODE_FULLDUPLEX;
speed = ETH_SPEED_10M;
break;
case LAN8742_STATUS_10MBITS_HALFDUPLEX:
duplex = ETH_MODE_HALFDUPLEX;
speed = ETH_SPEED_10M;
break;
default:
duplex = ETH_MODE_FULLDUPLEX;
speed = ETH_SPEED_100M;
break;
}
EthHandle.Init.Speed = speed;
EthHandle.Init.DuplexMode = duplex;
/* Configure Ethernet peripheral (GPIOs, clocks, MAC, DMA) */
if (HAL_ETH_Init(&EthHandle) != HAL_OK)
{
/* Return error. */
return(NX_DRIVER_ERROR);
}
/* Initialize TX Descriptors list: Ring Mode. */
/* Fill each DMATxDesc descriptor with the right values. */
for(i = 0; i < NX_DRIVER_TX_DESCRIPTORS; i++)
{
/* Get the pointer on the ith member of the Tx Desc list. */
DMATxDesc = &nx_driver_information.nx_driver_information_dma_tx_descriptors[i];
#ifdef HARDWARE_CHECKSUM_ENABLE
/* Set Second Address Chained bit and checksum offload options. */
DMATxDesc -> Status = ETH_DMATXDESC_TCH | ETH_DMATXDESC_IC | ETH_DMATXDESC_CIC_TCPUDPICMP_FULL | ETH_DMATXDESC_CIC_IPV4HEADER;
#else
/* Set Second Address Chained bit. */
DMATxDesc -> Status = ETH_DMATXDESC_TCH | ETH_DMATXDESC_IC;
#endif
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
if(i < (NX_DRIVER_TX_DESCRIPTORS - 1))
{
/* Set next descriptor address register with next descriptor base address */
DMATxDesc -> Buffer2NextDescAddr = (ULONG)(nx_driver_information.nx_driver_information_dma_tx_descriptors + i + 1);
}
else
{
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
DMATxDesc -> Buffer2NextDescAddr = (ULONG) nx_driver_information.nx_driver_information_dma_tx_descriptors;
}
}
/* Set Transmit Descriptor List Address Register */
ETH -> DMATDLAR = (ULONG) nx_driver_information.nx_driver_information_dma_tx_descriptors;
/* Initialize RX Descriptors list: Ring Mode */
/* Fill each DMARxDesc descriptor with the right values */
for(i = 0; i < NX_DRIVER_RX_DESCRIPTORS; i++)
{
/* Allocate a packet for the receive buffers. */
if (nx_packet_allocate(nx_driver_information.nx_driver_information_packet_pool_ptr, &packet_ptr,
NX_RECEIVE_PACKET, NX_NO_WAIT) == NX_SUCCESS)
{
/* Adjust the packet. */
packet_ptr -> nx_packet_prepend_ptr += 2;
DMARxDesc[i].Buffer1Addr = (uint32_t) packet_ptr -> nx_packet_prepend_ptr;
DMARxDesc[i].ControlBufferSize = ETH_DMARXDESC_RCH | (packet_ptr -> nx_packet_data_end - packet_ptr -> nx_packet_data_start);
/* Remember the receive packet poitner. */
nx_driver_information.nx_driver_information_receive_packets[i] = packet_ptr;
/* Set Own bit of the RX descriptor Status. */
DMARxDesc[i].Status = ETH_DMARXDESC_OWN;
}
else
{
/* Cannot allocate packets from the packet pool. */
return(NX_DRIVER_ERROR);
}
/* Initialize the next descriptor with the Next Descriptor Polling Enable. */
if(i < (NX_DRIVER_RX_DESCRIPTORS - 1))
{
/* Set next descriptor address register with next descriptor base address. */
DMARxDesc[i].Buffer2NextDescAddr = (ULONG)(nx_driver_information.nx_driver_information_dma_rx_descriptors + i + 1);
}
else
{
/* For last descriptor, set next descriptor address register equal to the first descriptor base address. */
DMARxDesc[i].Buffer2NextDescAddr = (uint32_t)(nx_driver_information.nx_driver_information_dma_rx_descriptors);
}
}
/* Save the size of one rx buffer. */
nx_driver_information.nx_driver_information_rx_buffer_size = packet_ptr -> nx_packet_data_end - packet_ptr -> nx_packet_data_start;
/* Clear the number of buffers in use counter. */
nx_driver_information.nx_driver_information_multicast_count = 0;
/* Set Receive Descriptor List Address Register */
ETH -> DMARDLAR = (ULONG) nx_driver_information.nx_driver_information_dma_rx_descriptors;
/* Return success! */
return(NX_SUCCESS);
头文件没动，但是LAN8742的内容全都加进去了 |
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发表于 2024-3-15 13:17:22
发表于 2024-3-16 09:36:23
