求助, zephyr点屏失败

O2C14

芯片是stm32h750, 开发板链接:STM32H750VB/H7B0VB核心板 - 立创开源硬件平台
屏幕是正点原子的480x272的屏.
下面是ltdc和pll的配置, clk_hse的频率是25M.参考了反客的配置,但是还是无法正常显示.

[C] 纯文本查看 复制代码

<dc {
	pinctrl-0 = <
        /*<dc_r0_pi15 <dc_r1_pj0 <dc_r2_pj1 */

		<dc_r3_pb0 <dc_r4_pa5 <dc_r5_pc0 <dc_r6_pb1 <dc_r7_pe15

		/* <dc_g0_pj7 <dc_g1_pj8 */

		<dc_g2_pa6 <dc_g3_pe11 <dc_g4_pb10 <dc_g5_pb11 <dc_g6_pc7 <dc_g7_pd3

		/*<dc_b0_pj12 <dc_b1_pj13 <dc_b2_pj14*/
		
		<dc_b3_pd10 <dc_b4_pe12 <dc_b5_pa3 <dc_b6_pb8 <dc_b7_pb9

		<dc_de_pe13 <dc_clk_pe14 <dc_hsync_pc6 <dc_vsync_pa4
        >;
	pinctrl-names = "default";
	disp-on-gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>;
	/delete-property/ ext-sdram;
	status = "okay";
	display-timings {
		compatible = "zephyr,panel-timing";
		de-active = <0>;
		pixelclk-active = <0>;
		hsync-active = <0>;
		vsync-active = <0>;
		hsync-len = <1>;
		vsync-len = <1>;
		hback-porch = <43>;
		vback-porch = <12>;
		hfront-porch = <8>;
		vfront-porch = <8>;
	};
};
&pll3 {
	div-m = <5>;
	mul-n = <192>;
	div-p = <2>;
	div-q = <20>;
	div-r = <96>;
	clocks = <&clk_hse>;
	status = "okay";
};

bricle

io时钟速率调为最高试一下，不一定有用哈，只是一个方向

eric2013

帮顶。

O2C14

刚下单一根新的排线, 再不行就放弃