RT1052 如何使用内部 RC 振荡器充当时钟源

castellan

我在 使用了 BOARD_BootClockRUN 函数后，用以下代码去切换内部晶振为，但是到了 切换函数这里后就失败了，程序直接死了，请问还有什么东西需要注意的吗？

1. CLOCK_RCStart();
   
2. CLOCK_InitRcOsc24M();
   
3. CLOCK_SwitchOsc(kCLOCK_RcOsc);

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eric2013

帮顶下，好久不搞，还真不会了。

castellan

这个已经弄好了。作如下修改就可以了

1. void BOARD_BootClockRUN(void)
   
2. {
   
3.     /* Enable 1MHz clock output. */
   
4.     XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
   
5.     /* Use free 1MHz clock output. */
   
6.     XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
   
7.     /* Set XTAL 24MHz clock frequency. */
   
8.     CLOCK_SetXtalFreq(24000000U);
   
9.     /* Enable XTAL 24MHz clock source. */
   
10.     CLOCK_InitExternalClk(0);
    
11.     /* Enable internal RC. */
    
12.     CLOCK_InitRcOsc24M();
    
13. 
    
14.     /* Configure self-tuning for RC OSC */
    
15.     XTALOSC24M->OSC_CONFIG0 = XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(0x4) | XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(0x2) |
    
16.                               XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(0xA7) |
    
17.                               XTALOSC24M_OSC_CONFIG0_START_MASK | XTALOSC24M_OSC_CONFIG0_ENABLE_MASK;
    
18.     XTALOSC24M->OSC_CONFIG1 = XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(0x40) | XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(0x2DC);
    
19.     /* Set Oscillator ready counter value. */
    
20.     CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
    
21.     /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
    
22.     CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
    
23.     CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
    
24.     /* Init ARM PLL. */
    
25.     /* Bypass PLL first. */
    
26.     CCM_ANALOG->PLL_ARM = (CCM_ANALOG->PLL_ARM & (~CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)) |
    
27.                           CCM_ANALOG_PLL_ARM_BYPASS_MASK | CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(0);
    
28.     CCM_ANALOG->PLL_ARM = (CCM_ANALOG->PLL_ARM & (~(CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK | CCM_ANALOG_PLL_ARM_POWERDOWN_MASK))) |
    
29.                           CCM_ANALOG_PLL_ARM_ENABLE_MASK | CCM_ANALOG_PLL_ARM_DIV_SELECT(98);
    
30.     while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0)
    
31.     {
    
32.     }
    
33.     /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
    
34.      * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
    
35.      * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
    
36. #ifndef SKIP_SYSCLK_INIT
    
37.     /* Init System PLL. */
    
38.     /* Bypass PLL first. */
    
39.     CCM_ANALOG->PLL_SYS = (CCM_ANALOG->PLL_SYS & (~CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)) |
    
40.                           CCM_ANALOG_PLL_SYS_BYPASS_MASK | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(0);
    
41.     CCM_ANALOG->PLL_SYS = (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) |
    
42.                           CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(1);
    
43.     while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0)
    
44.     {
    
45.     }
    
46.     /* Init System pfd0. */
    
47.     CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
    
48.     /* Init System pfd1. */
    
49.     CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
    
50.     /* Init System pfd2. */
    
51.     CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
    
52.     /* Init System pfd3. */
    
53.     CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
    
54.     /* Disable pfd offset. */
    
55.     CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
    
56. #endif
    
57.     /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
    
58.      * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
    
59.      * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
    
60. #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
    
61.     /* Set Usb1 PLL bypass clock source. */
    
62.     CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG, kCLOCK_PllUsb1, 0);
    
63.     /* DeInit Usb1 PLL. */
    
64.     CLOCK_DeinitUsb1Pll();
    
65.     /* Bypass Usb1 PLL. */
    
66.     CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_BYPASS_MASK;
    
67.     /* Enable Usb1 PLL output. */
    
68.     CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK;
    
69. #endif
    
70.     /* Set Audio PLL bypass clock source. */
    
71.     CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG, kCLOCK_PllAudio, 0);
    
72.     /* DeInit Audio PLL. */
    
73.     CLOCK_DeinitAudioPll();
    
74.     /* Bypass Audio PLL. */
    
75.     CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
    
76.     CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
    
77.     CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
    
78.     /* Enable Audio PLL output. */
    
79.     CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
    
80.     /* Set Video PLL bypass clock source. */
    
81.     CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG, kCLOCK_PllVideo, 0);
    
82.     /* DeInit Video PLL. */
    
83.     CLOCK_DeinitVideoPll();
    
84.     /* Bypass Video PLL. */
    
85.     CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
    
86.     CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
    
87.     /* Enable Video PLL output. */
    
88.     CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
    
89.     /* Init Enet PLL. */
    
90.     uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
    
91.     /* Bypass PLL first */
    
92.     CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)) |
    
93.                            CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(0);
    
94.     enet_pll |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
    
95.     enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
    
96.     CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | enet_pll;
    
97.     while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
    
98.     {
    
99.     }
    
100.     /* Disable pfd offset. */
     
101.     CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK;
     
102.     /* Set Usb2 PLL bypass clock source. */
     
103.     CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG, kCLOCK_PllUsb2, 0);
     
104.     /* DeInit Usb2 PLL. */
     
105.     CLOCK_DeinitUsb2Pll();
     
106.     /* Bypass Usb2 PLL. */
     
107.     CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_BYPASS_MASK;
     
108.     /* Enable Usb2 PLL output. */
     
109.     CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
     
110.     /* Set AHB_PODF. */
     
111.     CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
     
112.     /* Set IPG_PODF. */
     
113.     CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
     
114.     /* Set ARM_PODF. */
     
115.     CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
     
116.     /* Set preperiph clock source. */
     
117.     CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
     
118.     /* Set periph clock source. */
     
119.     CLOCK_SetMux(kCLOCK_PeriphMux, 0);
     
120.     /* Set PERIPH_CLK2_PODF. */
     
121.     CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
     
122.     /* Set periph clock2 clock source. */
     
123.     CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
     
124.     /* Set PERCLK_PODF. */
     
125.     CLOCK_SetDiv(kCLOCK_PerclkDiv, 0);
     
126.     /* Set per clock source. */
     
127.     CLOCK_SetMux(kCLOCK_PerclkMux, 0);
     
128.     /* Set USDHC1_PODF. */
     
129.     CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
     
130.     /* Set Usdhc1 clock source. */
     
131.     CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
     
132.     /* Set USDHC2_PODF. */
     
133.     CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
     
134.     /* Set Usdhc2 clock source. */
     
135.     CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
     
136.     /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
     
137.      * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
     
138.      * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
     
139. #ifndef SKIP_SYSCLK_INIT
     
140.     /* Set SEMC_PODF. */
     
141.     CLOCK_SetDiv(kCLOCK_SemcDiv, 2);
     
142.     /* Set Semc alt clock source. */
     
143.     CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
     
144.     /* Set Semc clock source. */
     
145.     CLOCK_SetMux(kCLOCK_SemcMux, 0);
     
146. #endif
     
147.     /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
     
148.      * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
     
149.      * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
     
150. #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
     
151.     /* Set FLEXSPI_PODF. */
     
152.     CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
     
153.     /* Set Flexspi clock source. */
     
154.     CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
     
155. #endif
     
156.     /* Set CSI_PODF. */
     
157.     CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
     
158.     /* Set Csi clock source. */
     
159.     CLOCK_SetMux(kCLOCK_CsiMux, 0);
     
160.     /* Set LPSPI_PODF. */
     
161.     CLOCK_SetDiv(kCLOCK_LpspiDiv, 3);
     
162.     /* Set Lpspi clock source. */
     
163.     CLOCK_SetMux(kCLOCK_LpspiMux, 2);
     
164.     /* Set TRACE_PODF. */
     
165.     CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
     
166.     /* Set Trace clock source. */
     
167.     CLOCK_SetMux(kCLOCK_TraceMux, 2);
     
168.     /* Set SAI1_CLK_PRED. */
     
169.     CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
     
170.     /* Set SAI1_CLK_PODF. */
     
171.     CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
     
172.     /* Set Sai1 clock source. */
     
173.     CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
     
174.     /* Set SAI2_CLK_PRED. */
     
175.     CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
     
176.     /* Set SAI2_CLK_PODF. */
     
177.     CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
     
178.     /* Set Sai2 clock source. */
     
179.     CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
     
180.     /* Set SAI3_CLK_PRED. */
     
181.     CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
     
182.     /* Set SAI3_CLK_PODF. */
     
183.     CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
     
184.     /* Set Sai3 clock source. */
     
185.     CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
     
186.     /* Set LPI2C_CLK_PODF. */
     
187.     CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
     
188.     /* Set Lpi2c clock source. */
     
189.     CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
     
190.     /* Set CAN_CLK_PODF. */
     
191.     CLOCK_SetDiv(kCLOCK_CanDiv, 1);
     
192.     /* Set Can clock source. */
     
193.     CLOCK_SetMux(kCLOCK_CanMux, 2);
     
194.     /* Set UART_CLK_PODF. */
     
195.     CLOCK_SetDiv(kCLOCK_UartDiv, 0);
     
196.     /* Set Uart clock source. */
     
197.     CLOCK_SetMux(kCLOCK_UartMux, 0);
     
198.     /* Set LCDIF_PRED. */
     
199.     CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
     
200.     /* Set LCDIF_CLK_PODF. */
     
201.     CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
     
202.     /* Set Lcdif pre clock source. */
     
203.     CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
     
204.     /* Set SPDIF0_CLK_PRED. */
     
205.     CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
     
206.     /* Set SPDIF0_CLK_PODF. */
     
207.     CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
     
208.     /* Set Spdif clock source. */
     
209.     CLOCK_SetMux(kCLOCK_SpdifMux, 3);
     
210.     /* Set FLEXIO1_CLK_PRED. */
     
211.     CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
     
212.     /* Set FLEXIO1_CLK_PODF. */
     
213.     CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
     
214.     /* Set Flexio1 clock source. */
     
215.     CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
     
216.     /* Set FLEXIO2_CLK_PRED. */
     
217.     CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
     
218.     /* Set FLEXIO2_CLK_PODF. */
     
219.     CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
     
220.     /* Set Flexio2 clock source. */
     
221.     CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
     
222.     /* Set Pll3 sw clock source. */
     
223.     CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
     
224.     /* Set lvds1 clock source. */
     
225.     CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
     
226.     /* Set clock out1 divider. */
     
227.     CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
     
228.     /* Set clock out1 source. */
     
229.     CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
     
230.     /* Set clock out2 divider. */
     
231.     CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
     
232.     /* Set clock out2 source. */
     
233.     CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
     
234.     /* Set clock out1 drives clock out1. */
     
235.     CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
     
236.     /* Disable clock out1. */
     
237.     CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
     
238.     /* Disable clock out2. */
     
239.     CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
     
240.     /* Set SystemCoreClock variable. */
     
241.     SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
     
242.             /* Switch clock source to internal RC. */
     
243.     CLOCK_SwitchOsc(kCLOCK_RcOsc);
     
244. }
     
245. 
     
246. 
     

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